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Lawrence Baranyai

Examiner (ID: 12458)

Most Active Art Unit
2665
Art Unit(s)
2665
Total Applications
1
Issued Applications
1
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14982207 [patent_doc_number] => 10445014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Methods of operating a computing system including a host processing data of first size and a storage device processing data of second size and including a memory controller and a non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/676651 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6120 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676651
Methods of operating a computing system including a host processing data of first size and a storage device processing data of second size and including a memory controller and a non-volatile memory Aug 13, 2017 Issued
Array ( [id] => 12844870 [patent_doc_number] => 20180173463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => HYBRID MEMORY ACCESS TO ON-CHIP MEMORY BY PARALLEL PROCESSING UNITS [patent_app_type] => utility [patent_app_number] => 15/675710 [patent_app_country] => US [patent_app_date] => 2017-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675710
Parallel memory access to on-chip memory containing regions of different addressing schemes by threads executed on parallel processing units Aug 11, 2017 Issued
Array ( [id] => 14034521 [patent_doc_number] => 10229012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Committing copy-on-write transaction with a persist barrier for a persistent object including payload references [patent_app_type] => utility [patent_app_number] => 15/675533 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 13457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675533 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675533
Committing copy-on-write transaction with a persist barrier for a persistent object including payload references Aug 10, 2017 Issued
Array ( [id] => 15373127 [patent_doc_number] => 10528281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Compressed freezer files [patent_app_type] => utility [patent_app_number] => 15/662908 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10362 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662908
Compressed freezer files Jul 27, 2017 Issued
Array ( [id] => 14669139 [patent_doc_number] => 10372470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Copy of memory information from a guest transmit descriptor from a free pool and assigned an intermediate state to a tracking data structure [patent_app_type] => utility [patent_app_number] => 15/648073 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10482 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/648073
Copy of memory information from a guest transmit descriptor from a free pool and assigned an intermediate state to a tracking data structure Jul 11, 2017 Issued
Array ( [id] => 13096677 [patent_doc_number] => 10067679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Avoiding out-of-space conditions in storage controllers [patent_app_type] => utility [patent_app_number] => 15/634191 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15634191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/634191
Avoiding out-of-space conditions in storage controllers Jun 26, 2017 Issued
Array ( [id] => 13601441 [patent_doc_number] => 20180352269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => PREFETCHER WITH ADAPTIVE STREAM SEGMENT PREFETCH WINDOW BASED ON CLIENT ASSOCIATED THRESHOLDS [patent_app_type] => utility [patent_app_number] => 15/614067 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614067
Prefetcher with adaptive stream segment prefetch window based on client associated thresholds Jun 4, 2017 Issued
Array ( [id] => 14411065 [patent_doc_number] => 20190171376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PERMISSION CONTROL FOR CONTINGENT MEMORY ACCESS PROGRAM INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/309190 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309190 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309190
Handling contingent and non-contingent memory access program instructions making use of disable flag May 17, 2017 Issued
Array ( [id] => 11945833 [patent_doc_number] => 20170249984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'MULTI-MODE MEMORY DEVICE AND METHOD HAVING STACKED MEMORY DICE, A LOGIC DIE AND A COMMAND PROCESSING CIRCUIT AND OPERATING IN DIRECT AND INDIRECT MODES' [patent_app_type] => utility [patent_app_number] => 15/597033 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597033 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597033
Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes May 15, 2017 Issued
Array ( [id] => 12207373 [patent_doc_number] => 20180052600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'DATA PROCESSING SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/476382 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476382
Data processing system with memory system using firmwares based on operating systems loaded into host and operating method thereof Mar 30, 2017 Issued
Array ( [id] => 13767089 [patent_doc_number] => 10175886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Systems and methods for handling missing storage image layers while provisioning containers in computer clusters [patent_app_type] => utility [patent_app_number] => 15/476343 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476343 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476343
Systems and methods for handling missing storage image layers while provisioning containers in computer clusters Mar 30, 2017 Issued
Array ( [id] => 16200752 [patent_doc_number] => 10725915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Methods and systems for maintaining cache coherency between caches of nodes in a clustered environment [patent_app_type] => utility [patent_app_number] => 15/476447 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476447
Methods and systems for maintaining cache coherency between caches of nodes in a clustered environment Mar 30, 2017 Issued
Array ( [id] => 14122939 [patent_doc_number] => 10248327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Throttling for a memory system using a GC/HOST ratio and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/476503 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9414 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476503
Throttling for a memory system using a GC/HOST ratio and operating method thereof Mar 30, 2017 Issued
Array ( [id] => 13403405 [patent_doc_number] => 20180253245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => PRE-BACKING VIRTUAL STORAGE USING LEARNING DATA [patent_app_type] => utility [patent_app_number] => 15/450297 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450297 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450297
Pre-backing virtual storage using historical learned data Mar 5, 2017 Issued
Array ( [id] => 11958052 [patent_doc_number] => 20170262205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'STORAGE DEVICE THAT CONTINUES A COMMAND OPERATION BEFORE NOTIFICATION OF AN ERROR CONDITION' [patent_app_type] => utility [patent_app_number] => 15/450667 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450667
Storage device that carries out parallel operations in response to host commands and upon detection of an error condition in one operation, continues the other operation before notification of the error condition is transmitted to the host Mar 5, 2017 Issued
Array ( [id] => 11973302 [patent_doc_number] => 20170277456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'APPARATUS AND METHOD TO REDUCE A RESPONSE TIME FOR WRITING DATA TO REDUNDANT STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 15/450289 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17907 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450289 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450289
Apparatus and method to reduce a response time for writing data to redundant storage devices by detecting completion of data-writing to at least one driver before elapse of a retry-over time Mar 5, 2017 Issued
Array ( [id] => 13807087 [patent_doc_number] => 10180810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Memory controller and storage device which selects memory devices in which data is to be written based on evaluation values of a usable capacity of the memory devices [patent_app_type] => utility [patent_app_number] => 15/450415 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 18142 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450415
Memory controller and storage device which selects memory devices in which data is to be written based on evaluation values of a usable capacity of the memory devices Mar 5, 2017 Issued
Array ( [id] => 11709008 [patent_doc_number] => 20170177507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'DATA READING/WRITING METHOD OF DUAL-SYSTEM TERMINAL AND DUAL-SYSTEM TERMINAL' [patent_app_type] => utility [patent_app_number] => 15/447835 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447835 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447835
DATA READING/WRITING METHOD OF DUAL-SYSTEM TERMINAL AND DUAL-SYSTEM TERMINAL Mar 1, 2017 Abandoned
Array ( [id] => 13639185 [patent_doc_number] => 09846551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => System on a chip including a management unit for allocating and deallocating an address range [patent_app_type] => utility [patent_app_number] => 15/427207 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 12326 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427207 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427207
System on a chip including a management unit for allocating and deallocating an address range Feb 7, 2017 Issued
Array ( [id] => 14669441 [patent_doc_number] => 10372622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Software controlled cache line replacement within a data property dependent cache segment of a cache using a cache segmentation enablement bit and cache segment selection bits [patent_app_type] => utility [patent_app_number] => 15/417302 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417302 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417302
Software controlled cache line replacement within a data property dependent cache segment of a cache using a cache segmentation enablement bit and cache segment selection bits Jan 26, 2017 Issued
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