Search

Lawrence Baranyai

Examiner (ID: 12458)

Most Active Art Unit
2665
Art Unit(s)
2665
Total Applications
1
Issued Applications
1
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11621728 [patent_doc_number] => 20170131915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS TO SEND PACKETIZED DATA OVER DIFFERENT ENDPOINTS OF A DATA HANDLING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/413732 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413732 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/413732
Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device Jan 23, 2017 Issued
Array ( [id] => 11996115 [patent_doc_number] => 20170300269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/398861 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398861
Memory system for re-ordering plural commands and operating method thereof Jan 4, 2017 Issued
Array ( [id] => 11823745 [patent_doc_number] => 20170212682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'TIME DE-INTERLEAVING CIRCUIT AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/399120 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4942 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399120 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399120
TIME DE-INTERLEAVING CIRCUIT AND METHOD THEREOF Jan 4, 2017 Abandoned
Array ( [id] => 11981845 [patent_doc_number] => 20170285999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'USING SEPARATE READ AND WRITE MEMORY DEVICES IN A DISTRIBUTED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/399022 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399022 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399022
Consolidating encoded data slices in read memory devices in a distributed storage network Jan 4, 2017 Issued
Array ( [id] => 12892042 [patent_doc_number] => 20180189189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => IMPLEMENTING PAGING DEVICE SELECTION BASED ON WEAR-LEVEL DATA [patent_app_type] => utility [patent_app_number] => 15/399484 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399484 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399484
Implementing paging device selection based on wear-level data Jan 4, 2017 Issued
Array ( [id] => 11982154 [patent_doc_number] => 20170286309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'WRITE CACHE SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/398979 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398979
Write cache acknowledgement system and method Jan 4, 2017 Issued
Array ( [id] => 11473635 [patent_doc_number] => 20170060418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'INFORMATION PROCESSING DEVICE INCLUDING HOST DEVICE AND SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF ADDRESS CONVERSION INFORMATION' [patent_app_type] => utility [patent_app_number] => 15/347528 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/347528
Information processing device including host device and semiconductor memory device having a block rearrangement to secure free blocks Nov 8, 2016 Issued
Array ( [id] => 14394921 [patent_doc_number] => 10310744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Memory system which transfers management information between first and second memories in a burst mode before a read process is performed on a third memory [patent_app_type] => utility [patent_app_number] => 15/336010 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/336010
Memory system which transfers management information between first and second memories in a burst mode before a read process is performed on a third memory Oct 26, 2016 Issued
Array ( [id] => 12590979 [patent_doc_number] => 20180088822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => USING COMPRESSION TO INCREASE CAPACITY OF A MEMORY-SIDE CACHE WITH LARGE BLOCK SIZE [patent_app_type] => utility [patent_app_number] => 15/279647 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279647
Replacement of a block with a compressed block to increase capacity of a memory-side cache Sep 28, 2016 Issued
Array ( [id] => 12591816 [patent_doc_number] => 20180089101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => COMPUTER PRODUCT, METHOD, AND SYSTEM TO PROVIDE A VIRTUAL TARGET TO VIRTUALIZE TARGET SYSTEM STORAGE RESOURCES AS VIRTUAL TARGET STORAGE RESOURCES [patent_app_type] => utility [patent_app_number] => 15/279318 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279318
Computer product, method, and system to provide discovery services to discover target storage resources and register a configuration of virtual target storage resources mapping to the target storage resources and an access control list of host nodes allowed to access the virtual target storage resources Sep 27, 2016 Issued
Array ( [id] => 13157807 [patent_doc_number] => 10095629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Local and remote dual address decoding using caching agent and switch [patent_app_type] => utility [patent_app_number] => 15/279319 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8848 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279319
Local and remote dual address decoding using caching agent and switch Sep 27, 2016 Issued
Array ( [id] => 12591741 [patent_doc_number] => 20180089076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => TECHNOLOGIES FOR COMBINING LOGICAL-TO-PHYSICAL ADDRESS UPDATES [patent_app_type] => utility [patent_app_number] => 15/278837 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278837 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278837
Technologies for combining logical-to-physical address table updates in a single write operation Sep 27, 2016 Issued
Array ( [id] => 12590925 [patent_doc_number] => 20180088804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => VIRTUALIZING NON-VOLATILE STORAGE AT A PERIPHERAL DEVICE [patent_app_type] => utility [patent_app_number] => 15/279352 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279352
Peripheral device providing virtualized non-volatile storage Sep 27, 2016 Issued
Array ( [id] => 12591735 [patent_doc_number] => 20180089074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Techniques to Manage Key-Value Storage at a Memory or Storage Device [patent_app_type] => utility [patent_app_number] => 15/279279 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/279279
Techniques to Manage Key-Value Storage at a Memory or Storage Device Sep 27, 2016 Abandoned
Array ( [id] => 12180501 [patent_doc_number] => 20180039437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD OF EXECUTING DATA SCRUBBING INSIDE A SMART STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/275337 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9919 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/275337
Method of executing conditional data scrubbing inside a smart storage device Sep 22, 2016 Issued
Array ( [id] => 11366114 [patent_doc_number] => 20170004095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'Memory Control Circuit and Storage Device' [patent_app_type] => utility [patent_app_number] => 15/266495 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266495
Memory Control Circuit and Storage Device Sep 14, 2016 Abandoned
Array ( [id] => 11365911 [patent_doc_number] => 20170003892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'STORAGE DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORIES WITH DIFFERENT CHARACTERISTICS, METHOD FOR CONTROLLING STORAGE DEVICE, AND COMPUTER-READABLE NONVOLATILE STORAGE MEDIUM FOR STORING PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/266771 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12205 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266771
Storage device, method, and computer-readable medium for selecting a write destination of target data to nonvolatile memories having different erase limits based upon a write interval Sep 14, 2016 Issued
Array ( [id] => 12290823 [patent_doc_number] => 09933948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Tiered storage system, computer using tiered storage device, and method of correcting count of accesses to file [patent_app_type] => utility [patent_app_number] => 15/265589 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 20440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265589
Tiered storage system, computer using tiered storage device, and method of correcting count of accesses to file Sep 13, 2016 Issued
Array ( [id] => 12207550 [patent_doc_number] => 20180052776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'Shared Virtual Index for Memory Object Fusion in Heterogeneous Cooperative Computing' [patent_app_type] => utility [patent_app_number] => 15/239937 [patent_app_country] => US [patent_app_date] => 2016-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15239937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/239937
Shared Virtual Index for Memory Object Fusion in Heterogeneous Cooperative Computing Aug 17, 2016 Abandoned
Array ( [id] => 12120827 [patent_doc_number] => 20180004413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'MAPPING TABLE UPDATING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/239771 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8914 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15239771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/239771
Mapping table updating method without updating the first mapping information, memory control circuit unit and memory storage device Aug 16, 2016 Issued
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