Lawrence Baranyai

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Array ( [id] => 12495033 [patent_doc_number] => 09996295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Semiconductor memory device having buffer/sensing circuit and scrambling/descrambling method thereof [patent_app_type] => utility [patent_app_number] => 15/239758 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6161 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15239758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11326871 [patent_doc_number] => 20160357483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'MEMORY SYSTEM FOR CONTROLLING READING FROM NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/238426 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15123 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11665132 [patent_doc_number] => 20170153851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'DATA UNIT CLASSIFICATION FOR SELECTIVE DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/226855 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10860 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14123465 [patent_doc_number] => 10248592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Interrupted write operation in a serial interface memory with a portion of a memory address [patent_app_type] => utility [patent_app_number] => 15/225562 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225562 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 12039368 [patent_doc_number] => 09817601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages' [patent_app_type] => utility [patent_app_number] => 15/204190 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204190 [rel_patent_id] =>[rel_patent_doc_number] =>)

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Array ( [id] => 11951247 [patent_doc_number] => 20170255398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'ADAPTIVE MECHANISM FOR SYNCHRONIZED OR ASYNCHRONIZED MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 15/174761 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5380 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174761 [rel_patent_id] =>[rel_patent_doc_number] =>)

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