
Lawrence C. Tynes Jr.
Examiner (ID: 17069, Phone: (571)270-7606 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2822, 2899, 4191, 2816 |
| Total Applications | 982 |
| Issued Applications | 796 |
| Pending Applications | 106 |
| Abandoned Applications | 117 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19531844
[patent_doc_number] => 20240355746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => ARCHITECTURE FOR COMPUTING SYSTEM PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/761884
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761884
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761884 | Architecture for computing system package | Jul 1, 2024 | Issued |
Array
(
[id] => 19531844
[patent_doc_number] => 20240355746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => ARCHITECTURE FOR COMPUTING SYSTEM PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/761884
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761884
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761884 | Architecture for computing system package | Jul 1, 2024 | Issued |
Array
(
[id] => 19531860
[patent_doc_number] => 20240355762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/760817
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760817
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760817 | Semiconductor Device and Method of Manufacture | Jun 30, 2024 | Pending |
Array
(
[id] => 19531860
[patent_doc_number] => 20240355762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/760817
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760817
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760817 | Semiconductor Device and Method of Manufacture | Jun 30, 2024 | Pending |
Array
(
[id] => 19531860
[patent_doc_number] => 20240355762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/760817
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760817
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760817 | Semiconductor Device and Method of Manufacture | Jun 30, 2024 | Pending |
Array
(
[id] => 19531852
[patent_doc_number] => 20240355754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => PACKAGES WITH THICK RDLS AND THIN RDLS STACKED ALTERNATINGLY
[patent_app_type] => utility
[patent_app_number] => 18/758423
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758423
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/758423 | PACKAGES WITH THICK RDLS AND THIN RDLS STACKED ALTERNATINGLY | Jun 27, 2024 | Pending |
Array
(
[id] => 19484156
[patent_doc_number] => 20240332198
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/740888
[patent_app_country] => US
[patent_app_date] => 2024-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740888
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/740888 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | Jun 11, 2024 | Pending |
Array
(
[id] => 19452793
[patent_doc_number] => 20240312923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/677075
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7722
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677075
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/677075 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | May 28, 2024 | Pending |
Array
(
[id] => 19452829
[patent_doc_number] => 20240312959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/675679
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675679 | SEMICONDUCTOR PACKAGE | May 27, 2024 | Pending |
Array
(
[id] => 19452829
[patent_doc_number] => 20240312959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/675679
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675679 | SEMICONDUCTOR PACKAGE | May 27, 2024 | Pending |
Array
(
[id] => 19468411
[patent_doc_number] => 20240322081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/656112
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20425
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656112
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/656112 | LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE HAVING THE SAME | May 5, 2024 | Pending |
Array
(
[id] => 19384824
[patent_doc_number] => 20240274694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => Integrated Circuit with a Fin and Gate Structure and Method Making the Same
[patent_app_type] => utility
[patent_app_number] => 18/635347
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9141
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635347
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/635347 | Integrated circuit with a Fin and gate structure and method making the same | Apr 14, 2024 | Issued |
Array
(
[id] => 20080847
[patent_doc_number] => 12354924
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Integrated circuit package and method
[patent_app_type] => utility
[patent_app_number] => 18/631966
[patent_app_country] => US
[patent_app_date] => 2024-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 6954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631966
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/631966 | Integrated circuit package and method | Apr 9, 2024 | Issued |
Array
(
[id] => 19349276
[patent_doc_number] => 20240258240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE
[patent_app_type] => utility
[patent_app_number] => 18/629424
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629424
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629424 | DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE | Apr 7, 2024 | Pending |
Array
(
[id] => 19305722
[patent_doc_number] => 20240234302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
[patent_app_type] => utility
[patent_app_number] => 18/617530
[patent_app_country] => US
[patent_app_date] => 2024-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14527
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617530
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/617530 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME | Mar 25, 2024 | Pending |
Array
(
[id] => 19285765
[patent_doc_number] => 20240222242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/609836
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7454
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609836
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609836 | GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE | Mar 18, 2024 | Pending |
Array
(
[id] => 19285765
[patent_doc_number] => 20240222242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/609836
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7454
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609836
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609836 | GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE | Mar 18, 2024 | Pending |
Array
(
[id] => 19285765
[patent_doc_number] => 20240222242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/609836
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7454
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609836
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609836 | GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE | Mar 18, 2024 | Pending |
Array
(
[id] => 19285631
[patent_doc_number] => 20240222108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => CONTROLLING THRESHOLD VOLTAGES THROUGH BLOCKING LAYERS
[patent_app_type] => utility
[patent_app_number] => 18/608560
[patent_app_country] => US
[patent_app_date] => 2024-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608560
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/608560 | CONTROLLING THRESHOLD VOLTAGES THROUGH BLOCKING LAYERS | Mar 17, 2024 | Pending |
Array
(
[id] => 19349348
[patent_doc_number] => 20240258312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/602033
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7932
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602033
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602033 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Mar 11, 2024 | Pending |