Search

Lawrence C. Tynes Jr.

Examiner (ID: 16074, Phone: (571)270-7606 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2822, 2816, 4191
Total Applications
1026
Issued Applications
836
Pending Applications
80
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18670004 [patent_doc_number] => 11776916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/199703 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 10682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199703
Semiconductor package Mar 11, 2021 Issued
Array ( [id] => 18704919 [patent_doc_number] => 11791438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Heterostructure for an optoelectronic device [patent_app_type] => utility [patent_app_number] => 17/198491 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 12122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198491
Heterostructure for an optoelectronic device Mar 10, 2021 Issued
Array ( [id] => 17431757 [patent_doc_number] => 20220059466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/198359 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198359
Semiconductor package and method of manufacturing the semiconductor package Mar 10, 2021 Issued
Array ( [id] => 17347167 [patent_doc_number] => 20220013498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/196470 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196470
Semiconductor package Mar 8, 2021 Issued
Array ( [id] => 16920789 [patent_doc_number] => 20210193881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => LIGHT EMITTING MODULE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/195417 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195417
Light emitting module and method of manufacturing the same Mar 7, 2021 Issued
Array ( [id] => 18935400 [patent_doc_number] => 11887841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Semiconductor packages [patent_app_type] => utility [patent_app_number] => 17/194575 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10500 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194575
Semiconductor packages Mar 7, 2021 Issued
Array ( [id] => 18704755 [patent_doc_number] => 11791272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Integrated circuits (ICs) with multi-row columnar die interconnects and IC packages including high density die-to-die (D2D) interconnects [patent_app_type] => utility [patent_app_number] => 17/191557 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9270 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191557
Integrated circuits (ICs) with multi-row columnar die interconnects and IC packages including high density die-to-die (D2D) interconnects Mar 2, 2021 Issued
Array ( [id] => 18073669 [patent_doc_number] => 11532508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Semiconductor device having contact layers and manufacturing method [patent_app_type] => utility [patent_app_number] => 17/184725 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 123 [patent_no_of_words] => 12796 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184725
Semiconductor device having contact layers and manufacturing method Feb 24, 2021 Issued
Array ( [id] => 17833672 [patent_doc_number] => 20220270976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES [patent_app_type] => utility [patent_app_number] => 17/183132 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183132
MICROELECTRONIC ASSEMBLIES INCLUDING BRIDGES Feb 22, 2021 Abandoned
Array ( [id] => 16889123 [patent_doc_number] => 20210175320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/181124 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181124
Organic light emitting display device Feb 21, 2021 Issued
Array ( [id] => 16936584 [patent_doc_number] => 20210202473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => MONOLITHIC SINGLE CHIP INTEGRATED RADIO FREQUENCY FRONT END MODULE CONFIGURED WITH SINGLE CRYSTAL ACOUSTIC FILTER DEVICES [patent_app_type] => utility [patent_app_number] => 17/180174 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180174
Monolithic single chip integrated radio frequency front end module configured with single crystal acoustic filter devices Feb 18, 2021 Issued
Array ( [id] => 19421011 [patent_doc_number] => 20240297135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SOLDER PASTE, METHOD FOR FORMING SOLDER BUMPS, AND METHOD FOR MANUFACTURING MEMBER PROVIDED WITH SOLDER BUMPS [patent_app_type] => utility [patent_app_number] => 18/263712 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18263712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/263712
SOLDER PASTE, METHOD FOR FORMING SOLDER BUMPS, AND METHOD FOR MANUFACTURING MEMBER PROVIDED WITH SOLDER BUMPS Feb 2, 2021 Pending
Array ( [id] => 18331832 [patent_doc_number] => 11637089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Semiconductor package including stacked semiconductor chips [patent_app_type] => utility [patent_app_number] => 17/154475 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11897 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154475
Semiconductor package including stacked semiconductor chips Jan 20, 2021 Issued
Array ( [id] => 17318912 [patent_doc_number] => 20210407962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/154789 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154789 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154789
Semiconductor package Jan 20, 2021 Issued
Array ( [id] => 17818734 [patent_doc_number] => 11424359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor device structure with high voltage device [patent_app_type] => utility [patent_app_number] => 17/142618 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142618 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142618
Semiconductor device structure with high voltage device Jan 5, 2021 Issued
Array ( [id] => 17708673 [patent_doc_number] => 20220208681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => STACK OF DIES [patent_app_type] => utility [patent_app_number] => 17/139388 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139388
Stack of dies Dec 30, 2020 Issued
Array ( [id] => 18670003 [patent_doc_number] => 11776915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => FPGA device forming network-on-chip by using silicon connection layer [patent_app_type] => utility [patent_app_number] => 17/294985 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3573 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17294985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/294985
FPGA device forming network-on-chip by using silicon connection layer Dec 29, 2020 Issued
Array ( [id] => 18121065 [patent_doc_number] => 11552468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Electrical device with power quality event protection and associated method [patent_app_type] => utility [patent_app_number] => 17/137704 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137704
Electrical device with power quality event protection and associated method Dec 29, 2020 Issued
Array ( [id] => 16782025 [patent_doc_number] => 20210119104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ELECTRICAL LEADS FOR TRENCHED QUBITS [patent_app_type] => utility [patent_app_number] => 17/135584 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135584
Electrical leads for trenched qubits Dec 27, 2020 Issued
Array ( [id] => 17692224 [patent_doc_number] => 20220199517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DIE STITCHING AND HARVESTING OF ARRAYED STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/133096 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133096
Die stitching and harvesting of arrayed structures Dec 22, 2020 Issued
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