Search

Lawrence C. Tynes Jr.

Examiner (ID: 16074, Phone: (571)270-7606 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2899, 2822, 2816, 4191
Total Applications
1026
Issued Applications
836
Pending Applications
80
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15653013 [patent_doc_number] => 20200089037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE WITH TOUCH SENSOR [patent_app_type] => utility [patent_app_number] => 16/571325 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 590 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571325
Method for manufacturing active matrix substrate and method for manufacturing liquid crystal display device with touch sensor Sep 15, 2019 Issued
Array ( [id] => 17353303 [patent_doc_number] => 11227950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Methods of forming air spacers in semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/572320 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572320
Methods of forming air spacers in semiconductor devices Sep 15, 2019 Issued
Array ( [id] => 16715547 [patent_doc_number] => 20210082694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Controlling Threshold Voltages Through Blocking Layers [patent_app_type] => utility [patent_app_number] => 16/571944 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571944 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571944
Controlling threshold voltages through blocking layers Sep 15, 2019 Issued
Array ( [id] => 15332367 [patent_doc_number] => 20200006513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Metal Gate Process for FinFET Device Improvement [patent_app_type] => utility [patent_app_number] => 16/570686 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570686
Metal gate process for FinFET device improvement Sep 12, 2019 Issued
Array ( [id] => 18958964 [patent_doc_number] => 20240047291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => HIGH DENSITY PLASMA CVD FOR DISPLAY ENCAPSULATION APPLICATION [patent_app_type] => utility [patent_app_number] => 17/641365 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17641365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/641365
HIGH DENSITY PLASMA CVD FOR DISPLAY ENCAPSULATION APPLICATION Sep 9, 2019 Pending
Array ( [id] => 15300415 [patent_doc_number] => 20190393343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => CLOSE PROXIMITY AND LATERAL RESISTANCE REDUCTION FOR BOTTOM SOURCE/DRAIN EPITAXY IN VERTICAL TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/553812 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553812
Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices Aug 27, 2019 Issued
Array ( [id] => 15718149 [patent_doc_number] => 20200105842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, ADJUSTMENT METHOD AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/550135 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550135
DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, ADJUSTMENT METHOD AND DISPLAY DEVICE Aug 22, 2019 Abandoned
Array ( [id] => 16264641 [patent_doc_number] => 10756088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Method and structure of forming strained channels for CMOS device fabrication [patent_app_type] => utility [patent_app_number] => 16/541276 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 8507 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541276
Method and structure of forming strained channels for CMOS device fabrication Aug 14, 2019 Issued
Array ( [id] => 15184981 [patent_doc_number] => 20190363082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => METHOD AND STRUCTURE OF FORMING STRAINED CHANNELS FOR CMOS DEVICE FABRICATION [patent_app_type] => utility [patent_app_number] => 16/539738 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539738
Forming strained channels for CMOS device fabrication Aug 12, 2019 Issued
Array ( [id] => 16625377 [patent_doc_number] => 20210044030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => BRIDGE FOR RADIO FREQUENCY (RF) MULTI-CHIP MODULES [patent_app_type] => utility [patent_app_number] => 16/534820 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534820
Bridge for radio frequency (RF) multi-chip modules Aug 6, 2019 Issued
Array ( [id] => 15218211 [patent_doc_number] => 20190371792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => MONOLITHIC SINGLE CHIP INTEGRATED RADIO FREQUENCY FRONT END MODULE CONFIGURED WITH SINGLE CRYSTAL ACOUSTIC FILTER DEVICES [patent_app_type] => utility [patent_app_number] => 16/532333 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532333 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532333
Monolithic single chip integrated radio frequency front end module configured with single crystal acoustic filter devices Aug 4, 2019 Issued
Array ( [id] => 17166153 [patent_doc_number] => 11152265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors [patent_app_type] => utility [patent_app_number] => 16/528748 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528748 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528748
Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors Jul 31, 2019 Issued
Array ( [id] => 17063138 [patent_doc_number] => 11107748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Semiconductor module and vehicle [patent_app_type] => utility [patent_app_number] => 16/528657 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12715 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528657
Semiconductor module and vehicle Jul 31, 2019 Issued
Array ( [id] => 15462593 [patent_doc_number] => 20200044121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => LIGHT EMITTING MODULE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/529005 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529005
Light emitting module and method of manufacturing the same Jul 31, 2019 Issued
Array ( [id] => 17745630 [patent_doc_number] => 11393711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Silicon oxide layer for oxidation resistance and method forming same [patent_app_type] => utility [patent_app_number] => 16/528875 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 36 [patent_no_of_words] => 9637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528875
Silicon oxide layer for oxidation resistance and method forming same Jul 31, 2019 Issued
Array ( [id] => 18481194 [patent_doc_number] => 11694949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/529194 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5702 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529194 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529194
Semiconductor package and method of manufacturing the same Jul 31, 2019 Issued
Array ( [id] => 16928346 [patent_doc_number] => 11049837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Bond wire array for packaged semiconductor device [patent_app_type] => utility [patent_app_number] => 16/528389 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9959 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528389 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528389
Bond wire array for packaged semiconductor device Jul 30, 2019 Issued
Array ( [id] => 18236002 [patent_doc_number] => 11600567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/528352 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7847 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528352
Semiconductor device package and method for manufacturing the same Jul 30, 2019 Issued
Array ( [id] => 17174435 [patent_doc_number] => 20210328106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => OPTOELECTRONIC SEMICONDUCTOR COMPONENT WITH A CURRENT SPREADING STRUCTURE CONTAINING SILVER, AND OPTOELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/258757 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17258757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/258757
Optoelectronic semiconductor component with a current spreading structure containing silver, and optoelectronic device Jul 10, 2019 Issued
Array ( [id] => 15030233 [patent_doc_number] => 20190326121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => MANUFACTURING METHOD OF HIGH-DIELECTRIC-CONSTANT GATE INSULATING FILM OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/459067 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459067
Manufacturing method of high-dielectric-constant gate insulating film of semiconductor device Jun 30, 2019 Issued
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