
Lawrence C. Tynes Jr.
Examiner (ID: 16074, Phone: (571)270-7606 , Office: P/2816 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2822, 2816, 4191 |
| Total Applications | 1026 |
| Issued Applications | 836 |
| Pending Applications | 80 |
| Abandoned Applications | 120 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16593805
[patent_doc_number] => 10903082
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-26
[patent_title] => Spacer sculpting for forming semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 16/251856
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 5802
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251856
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/251856 | Spacer sculpting for forming semiconductor devices | Jan 17, 2019 | Issued |
Array
(
[id] => 14631287
[patent_doc_number] => 20190229013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => Semiconductor Device Including First and Second Contact Layers and Manufacturing Method
[patent_app_type] => utility
[patent_app_number] => 16/251729
[patent_app_country] => US
[patent_app_date] => 2019-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12796
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251729
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/251729 | Semiconductor device including first and second contact layers and manufacturing method | Jan 17, 2019 | Issued |
Array
(
[id] => 14587681
[patent_doc_number] => 20190221449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => Semiconductor Module and Method for Producing the Same
[patent_app_type] => utility
[patent_app_number] => 16/248295
[patent_app_country] => US
[patent_app_date] => 2019-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4806
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248295
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/248295 | Semiconductor module and method for producing the same | Jan 14, 2019 | Issued |
Array
(
[id] => 14317205
[patent_doc_number] => 20190148306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => SEMICONDUCTOR BACKMETAL AND OVER PAD METALLIZATION STRUCTURES AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 16/229186
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8106
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229186
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/229186 | SEMICONDUCTOR BACKMETAL AND OVER PAD METALLIZATION STRUCTURES AND RELATED METHODS | Dec 20, 2018 | Abandoned |
Array
(
[id] => 15170229
[patent_doc_number] => 10490620
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-11-26
[patent_title] => Array substrate, display panel and display device
[patent_app_type] => utility
[patent_app_number] => 16/229287
[patent_app_country] => US
[patent_app_date] => 2018-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7013
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 385
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229287
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/229287 | Array substrate, display panel and display device | Dec 20, 2018 | Issued |
Array
(
[id] => 16690253
[patent_doc_number] => 20210072731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => DEVICE AND METHOD FOR OBTAINING INFORMATION ABOUT LAYERS DEPOSITED IN A CVD METHOD
[patent_app_type] => utility
[patent_app_number] => 16/955667
[patent_app_country] => US
[patent_app_date] => 2018-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8868
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16955667
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/955667 | Device and method for obtaining information about layers deposited in a CVD method | Dec 12, 2018 | Issued |
Array
(
[id] => 16148601
[patent_doc_number] => 10707382
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-07
[patent_title] => Light emitting element
[patent_app_type] => utility
[patent_app_number] => 16/218042
[patent_app_country] => US
[patent_app_date] => 2018-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 99
[patent_no_of_words] => 31515
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218042
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/218042 | Light emitting element | Dec 11, 2018 | Issued |
Array
(
[id] => 16560397
[patent_doc_number] => 20210005546
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => ELECTRONIC ASSEMBLY HAVING MULTIPLE SUBSTRATE SEGMENTS
[patent_app_type] => utility
[patent_app_number] => 16/766616
[patent_app_country] => US
[patent_app_date] => 2018-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3934
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16766616
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/766616 | Electronic assembly having multiple substrate segments | Nov 29, 2018 | Issued |
Array
(
[id] => 16638173
[patent_doc_number] => 10916690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Electrical leads for trenched qubits
[patent_app_type] => utility
[patent_app_number] => 16/202828
[patent_app_country] => US
[patent_app_date] => 2018-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 20774
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202828
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/202828 | Electrical leads for trenched qubits | Nov 27, 2018 | Issued |
Array
(
[id] => 17239755
[patent_doc_number] => 11183650
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Display substrate, method of manufacturing the same, and display device including the same
[patent_app_type] => utility
[patent_app_number] => 16/202595
[patent_app_country] => US
[patent_app_date] => 2018-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5997
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202595
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/202595 | Display substrate, method of manufacturing the same, and display device including the same | Nov 27, 2018 | Issued |
Array
(
[id] => 14631205
[patent_doc_number] => 20190228971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => DOPING SYSTEM, DOPING METHOD AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/201479
[patent_app_country] => US
[patent_app_date] => 2018-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201479
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/201479 | Doping system, doping method and method for manufacturing silicon carbide semiconductor device | Nov 26, 2018 | Issued |
Array
(
[id] => 14024613
[patent_doc_number] => 20190074300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-07
[patent_title] => ORTHOGONAL TRANSISTOR LAYOUTS
[patent_app_type] => utility
[patent_app_number] => 16/182609
[patent_app_country] => US
[patent_app_date] => 2018-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182609
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/182609 | Orthogonal transistor layouts | Nov 6, 2018 | Issued |
Array
(
[id] => 15955211
[patent_doc_number] => 10665520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-26
[patent_title] => Integrated circuit package and method
[patent_app_type] => utility
[patent_app_number] => 16/173488
[patent_app_country] => US
[patent_app_date] => 2018-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 11816
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173488
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/173488 | Integrated circuit package and method | Oct 28, 2018 | Issued |
Array
(
[id] => 16566983
[patent_doc_number] => 10892360
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-12
[patent_title] => Semiconductor device structure with high voltage device
[patent_app_type] => utility
[patent_app_number] => 16/173721
[patent_app_country] => US
[patent_app_date] => 2018-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173721
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/173721 | Semiconductor device structure with high voltage device | Oct 28, 2018 | Issued |
Array
(
[id] => 16201945
[patent_doc_number] => 10727124
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Structure and method for forming fully-aligned trench with an up-via integration scheme
[patent_app_type] => utility
[patent_app_number] => 16/173327
[patent_app_country] => US
[patent_app_date] => 2018-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3609
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173327
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/173327 | Structure and method for forming fully-aligned trench with an up-via integration scheme | Oct 28, 2018 | Issued |
Array
(
[id] => 16201967
[patent_doc_number] => 10727146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/173598
[patent_app_country] => US
[patent_app_date] => 2018-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3621
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173598
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/173598 | Semiconductor device | Oct 28, 2018 | Issued |
Array
(
[id] => 18219570
[patent_doc_number] => 11594519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/770786
[patent_app_country] => US
[patent_app_date] => 2018-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4199
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16770786
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/770786 | Semiconductor device | Oct 4, 2018 | Issued |
Array
(
[id] => 16594080
[patent_doc_number] => 10903357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-26
[patent_title] => Laterally diffused metal oxide semiconductor (LDMOS) transistor on a semiconductor on insulator (SOI) layer with a backside device
[patent_app_type] => utility
[patent_app_number] => 16/152105
[patent_app_country] => US
[patent_app_date] => 2018-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8039
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152105
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/152105 | Laterally diffused metal oxide semiconductor (LDMOS) transistor on a semiconductor on insulator (SOI) layer with a backside device | Oct 3, 2018 | Issued |
Array
(
[id] => 15985103
[patent_doc_number] => 10672891
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Stacked gate all around MOSFET with symmetric inner spacer formed via sacrificial pure Si anchors
[patent_app_type] => utility
[patent_app_number] => 16/152022
[patent_app_country] => US
[patent_app_date] => 2018-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 3042
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152022
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/152022 | Stacked gate all around MOSFET with symmetric inner spacer formed via sacrificial pure Si anchors | Oct 3, 2018 | Issued |
Array
(
[id] => 15745813
[patent_doc_number] => 20200111796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-09
[patent_title] => Methods of Forming Integrated Assemblies
[patent_app_type] => utility
[patent_app_number] => 16/152129
[patent_app_country] => US
[patent_app_date] => 2018-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152129
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/152129 | Methods of forming integrated assemblies | Oct 3, 2018 | Issued |