Search

Lawrence C. Tynes Jr.

Examiner (ID: 17069, Phone: (571)270-7606 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2822, 2899, 4191, 2816
Total Applications
982
Issued Applications
796
Pending Applications
106
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18350213 [patent_doc_number] => 20230138324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => PACKAGE-LEVEL ESD PROTECTION [patent_app_type] => utility [patent_app_number] => 17/902912 [patent_app_country] => US [patent_app_date] => 2022-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902912
PACKAGE-LEVEL ESD PROTECTION Sep 4, 2022 Pending
Array ( [id] => 18585992 [patent_doc_number] => 20230268257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => ELECTRONIC PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/902902 [patent_app_country] => US [patent_app_date] => 2022-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902902
ELECTRONIC PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Sep 4, 2022 Issued
Array ( [id] => 19007707 [patent_doc_number] => 20240071778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR INTERCONNECT BRIDGE PACKAGING [patent_app_type] => utility [patent_app_number] => 17/900153 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900153
SEMICONDUCTOR INTERCONNECT BRIDGE PACKAGING Aug 30, 2022 Pending
Array ( [id] => 19007866 [patent_doc_number] => 20240071937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR INTERCONNECT BRIDGE PACKAGING [patent_app_type] => utility [patent_app_number] => 17/900033 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900033
SEMICONDUCTOR INTERCONNECT BRIDGE PACKAGING Aug 30, 2022 Pending
Array ( [id] => 18061755 [patent_doc_number] => 20220392842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE [patent_app_type] => utility [patent_app_number] => 17/888177 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888177
Device and method of very high density routing used with embedded multi-die interconnect bridge Aug 14, 2022 Issued
Array ( [id] => 18311173 [patent_doc_number] => 20230115073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/815634 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815634
SEMICONDUCTOR PACKAGE Jul 27, 2022 Pending
Array ( [id] => 18688396 [patent_doc_number] => 11784140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/815338 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 13843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815338
Semiconductor device and method of manufacture Jul 26, 2022 Issued
Array ( [id] => 19670929 [patent_doc_number] => 12183700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor device package and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/874402 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874402
Semiconductor device package and method of manufacture Jul 26, 2022 Issued
Array ( [id] => 17993366 [patent_doc_number] => 20220359403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Packages with Thick RDLs and Thin RDLs Stacked Alternatingly [patent_app_type] => utility [patent_app_number] => 17/814730 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814730
Packages with thick RDLs and thin RDLs stacked alternatingly Jul 24, 2022 Issued
Array ( [id] => 17993156 [patent_doc_number] => 20220359193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Controlling Threshold Voltages Through Blocking Layers [patent_app_type] => utility [patent_app_number] => 17/814716 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814716
Controlling threshold voltages through blocking layers Jul 24, 2022 Issued
Array ( [id] => 17993318 [patent_doc_number] => 20220359355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => GIGA INTERPOSER INTEGRATION THROUGH CHIP-ON-WAFER-ON-SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/870099 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870099
Giga interposer integration through Chip-On-Wafer-On-Substrate Jul 20, 2022 Issued
Array ( [id] => 17993399 [patent_doc_number] => 20220359436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Connector Formation Methods and Packaged Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/869080 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869080
Connector Formation Methods and Packaged Semiconductor Devices Jul 19, 2022 Pending
Array ( [id] => 19906558 [patent_doc_number] => 12283577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Fan-out semiconductor package [patent_app_type] => utility [patent_app_number] => 17/862482 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862482
Fan-out semiconductor package Jul 11, 2022 Issued
Array ( [id] => 19964936 [patent_doc_number] => 12334456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Electronic package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/858905 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858905
Electronic package and manufacturing method thereof Jul 5, 2022 Issued
Array ( [id] => 19582524 [patent_doc_number] => 12148652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Silicon oxide layer for oxidation resistance and method forming same [patent_app_type] => utility [patent_app_number] => 17/809921 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 36 [patent_no_of_words] => 9497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809921
Silicon oxide layer for oxidation resistance and method forming same Jun 29, 2022 Issued
Array ( [id] => 18639551 [patent_doc_number] => 11764173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor package for high-speed data transmission and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/809903 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 13311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809903
Semiconductor package for high-speed data transmission and manufacturing method thereof Jun 29, 2022 Issued
Array ( [id] => 18882920 [patent_doc_number] => 20240006289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => LOW INSERTION LOSS COAXIAL THROUGH-HOLE FOR HIGHSPEED INPUT-OUPUT [patent_app_type] => utility [patent_app_number] => 17/853204 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853204 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853204
LOW INSERTION LOSS COAXIAL THROUGH-HOLE FOR HIGHSPEED INPUT-OUPUT Jun 28, 2022 Pending
Array ( [id] => 18882920 [patent_doc_number] => 20240006289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => LOW INSERTION LOSS COAXIAL THROUGH-HOLE FOR HIGHSPEED INPUT-OUPUT [patent_app_type] => utility [patent_app_number] => 17/853204 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853204 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853204
LOW INSERTION LOSS COAXIAL THROUGH-HOLE FOR HIGHSPEED INPUT-OUPUT Jun 28, 2022 Pending
Array ( [id] => 19208104 [patent_doc_number] => 20240180003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/790247 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790247
Display panel Jun 28, 2022 Issued
Array ( [id] => 17949640 [patent_doc_number] => 20220336659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH HIGH VOLTAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/852802 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852802
Semiconductor device structure with high voltage device Jun 28, 2022 Issued
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