Search

Lawrence C. Tynes Jr.

Examiner (ID: 17069, Phone: (571)270-7606 , Office: P/2816 )

Most Active Art Unit
2816
Art Unit(s)
2822, 2899, 4191, 2816
Total Applications
982
Issued Applications
796
Pending Applications
106
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18416054 [patent_doc_number] => 11670602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Secure integrated-circuit systems [patent_app_type] => utility [patent_app_number] => 17/569085 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569085
Secure integrated-circuit systems Jan 4, 2022 Issued
Array ( [id] => 17551555 [patent_doc_number] => 20220122897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Integrated Circuit Package and Method [patent_app_type] => utility [patent_app_number] => 17/567519 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567519
Integrated circuit package and method Jan 2, 2022 Issued
Array ( [id] => 19063145 [patent_doc_number] => 11942396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Heterogeneous integration semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/564219 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 5471 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564219
Heterogeneous integration semiconductor package structure Dec 28, 2021 Issued
Array ( [id] => 18040134 [patent_doc_number] => 20220384351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/562477 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562477
Semiconductor device and semiconductor package including the same Dec 26, 2021 Issued
Array ( [id] => 18473117 [patent_doc_number] => 20230207405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES [patent_app_type] => utility [patent_app_number] => 17/561722 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561722
ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES Dec 23, 2021 Pending
Array ( [id] => 18473119 [patent_doc_number] => 20230207407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PLATE-UP HYBRID STRUCTURES USING MODIFIED GLASS PATTERNING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/561734 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561734
PLATE-UP HYBRID STRUCTURES USING MODIFIED GLASS PATTERNING PROCESSES Dec 23, 2021 Pending
Array ( [id] => 18473151 [patent_doc_number] => 20230207439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES [patent_app_type] => utility [patent_app_number] => 17/561533 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561533
PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES Dec 22, 2021 Pending
Array ( [id] => 18473124 [patent_doc_number] => 20230207412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => TECHNIQUES TO ENABLE A FLIP CHIP UNDERFILL EXCLUSION ZONE [patent_app_type] => utility [patent_app_number] => 17/561432 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561432
TECHNIQUES TO ENABLE A FLIP CHIP UNDERFILL EXCLUSION ZONE Dec 22, 2021 Pending
Array ( [id] => 18473151 [patent_doc_number] => 20230207439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES [patent_app_type] => utility [patent_app_number] => 17/561533 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561533
PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES Dec 22, 2021 Pending
Array ( [id] => 18473231 [patent_doc_number] => 20230207519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SEMICONDUCTOR DEVICE WITH COMPOSITE BOTTOM INTERCONNECTORS [patent_app_type] => utility [patent_app_number] => 17/560596 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560596
Semiconductor device with composite bottom interconnectors Dec 22, 2021 Issued
Array ( [id] => 17708724 [patent_doc_number] => 20220208732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MULTI-DIE CO-PACKED MODULE AND MULTI-DIE CO-PACKING METHOD [patent_app_type] => utility [patent_app_number] => 17/545282 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545282
MULTI-DIE CO-PACKED MODULE AND MULTI-DIE CO-PACKING METHOD Dec 7, 2021 Abandoned
Array ( [id] => 17660823 [patent_doc_number] => 20220181288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING A DUALIZED SIGNAL WIRING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/542667 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542667
Semiconductor package including a dualized signal wiring structure Dec 5, 2021 Issued
Array ( [id] => 17645266 [patent_doc_number] => 20220173005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly [patent_app_type] => utility [patent_app_number] => 17/535986 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535986
Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly Nov 25, 2021 Issued
Array ( [id] => 18249031 [patent_doc_number] => 11605629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Method for preparing semiconductor device structure with series-connected transistor and resistor [patent_app_type] => utility [patent_app_number] => 17/520544 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8380 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520544
Method for preparing semiconductor device structure with series-connected transistor and resistor Nov 4, 2021 Issued
Array ( [id] => 17417015 [patent_doc_number] => 20220051919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => CONTROL OF WAFER BOW IN MULTIPLE STATIONS [patent_app_type] => utility [patent_app_number] => 17/515261 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515261
Control of wafer bow in multiple stations Oct 28, 2021 Issued
Array ( [id] => 19029991 [patent_doc_number] => 11929357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Optoelectronic package structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/506462 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6201 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506462
Optoelectronic package structure and method of manufacturing the same Oct 19, 2021 Issued
Array ( [id] => 17551582 [patent_doc_number] => 20220122924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => INTEGRATED SELF-ALIGNED ASSEMBLY [patent_app_type] => utility [patent_app_number] => 17/504125 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504125
Integrated self-aligned assembly Oct 17, 2021 Issued
Array ( [id] => 18593335 [patent_doc_number] => 11742246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors [patent_app_type] => utility [patent_app_number] => 17/502210 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502210
Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors Oct 14, 2021 Issued
Array ( [id] => 19912531 [patent_doc_number] => 12288750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Conformal power delivery structure for direct chip attach architectures [patent_app_type] => utility [patent_app_number] => 17/485208 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6923 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485208
Conformal power delivery structure for direct chip attach architectures Sep 23, 2021 Issued
Array ( [id] => 17692227 [patent_doc_number] => 20220199520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/476670 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476670
Semiconductor package and method of manufacturing the semiconductor package Sep 15, 2021 Issued
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