Search

Lawrence D. Ferguson

Examiner (ID: 15259)

Most Active Art Unit
1781
Art Unit(s)
1781, 1774, 1783, 1794
Total Applications
1565
Issued Applications
1059
Pending Applications
146
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20003430 [patent_doc_number] => 20250141652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => CLOCK RECOVERY TRAINING [patent_app_type] => utility [patent_app_number] => 19/010319 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19010319 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/010319
CLOCK RECOVERY TRAINING Jan 5, 2025 Pending
Array ( [id] => 20051818 [patent_doc_number] => 20250190040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => ELECTRONIC APPARATUS AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/974484 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974484
ELECTRONIC APPARATUS AND CONTROL METHOD Dec 8, 2024 Pending
Array ( [id] => 20034768 [patent_doc_number] => 20250172990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SYSTEM-ON-CHIP AND POWER MANAGEMENT METHOD FOR SUCH A SYSTEM-ON-CHIP [patent_app_type] => utility [patent_app_number] => 18/959060 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959060 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/959060
SYSTEM-ON-CHIP AND POWER MANAGEMENT METHOD FOR SUCH A SYSTEM-ON-CHIP Nov 24, 2024 Pending
Array ( [id] => 19802506 [patent_doc_number] => 20250068431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SYSTEM-ON-CHIP FOR SHARING GRAPHICS PROCESSING UNIT THAT SUPPORTS MULTIMASTER, AND METHOD FOR OPERATING GRAPHICS PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/947754 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/947754
SYSTEM-ON-CHIP FOR SHARING GRAPHICS PROCESSING UNIT THAT SUPPORTS MULTIMASTER, AND METHOD FOR OPERATING GRAPHICS PROCESSING UNIT Nov 13, 2024 Pending
Array ( [id] => 19802295 [patent_doc_number] => 20250068220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => CALIBRATION OF RESOURCE SERVER POWER ALLOCATIONS WITHIN A DATA STORAGE DEVICE USING CONFORMAL PREDICTIONS [patent_app_type] => utility [patent_app_number] => 18/941572 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941572
CALIBRATION OF RESOURCE SERVER POWER ALLOCATIONS WITHIN A DATA STORAGE DEVICE USING CONFORMAL PREDICTIONS Nov 7, 2024 Pending
Array ( [id] => 19878283 [patent_doc_number] => 20250110540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => POWER MANAGEMENT INTEGRATED CIRCUIT DEVICE HAVING MULTIPLE INITIALIZATION/POWER UP MODES [patent_app_type] => utility [patent_app_number] => 18/916160 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18916160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/916160
POWER MANAGEMENT INTEGRATED CIRCUIT DEVICE HAVING MULTIPLE INITIALIZATION/POWER UP MODES Oct 14, 2024 Pending
Array ( [id] => 20640811 [patent_doc_number] => 20260099167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-09 [patent_title] => POWER VOLTAGE PHASE ADJUSTMENT FOR ADAPTIVE CLOCK DISTRIBUTION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/909356 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909356
POWER VOLTAGE PHASE ADJUSTMENT FOR ADAPTIVE CLOCK DISTRIBUTION SYSTEM Oct 7, 2024 Pending
Array ( [id] => 20375611 [patent_doc_number] => 12483056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Charging system for prioritized power distribution and dynamic power adjustment [patent_app_type] => utility [patent_app_number] => 18/899243 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2302 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18899243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/899243
Charging system for prioritized power distribution and dynamic power adjustment Sep 26, 2024 Issued
18/847348 DEVICE AND POWER CONTROL METHOD AND APPARATUS FOR DEVICE Sep 15, 2024 Pending
Array ( [id] => 19685951 [patent_doc_number] => 20250004496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MULTI-PHASE SIGNAL GENERATION [patent_app_type] => utility [patent_app_number] => 18/884635 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18884635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/884635
MULTI-PHASE SIGNAL GENERATION Sep 12, 2024 Pending
Array ( [id] => 19833974 [patent_doc_number] => 20250085760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/826795 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826795
COMMUNICATION SYSTEM Sep 5, 2024 Pending
Array ( [id] => 19644690 [patent_doc_number] => 20240419210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES [patent_app_type] => utility [patent_app_number] => 18/819437 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819437
SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES Aug 28, 2024 Pending
Array ( [id] => 19558259 [patent_doc_number] => 20240370051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => ASYNCHRONOUS ASIC [patent_app_type] => utility [patent_app_number] => 18/773471 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773471
ASYNCHRONOUS ASIC Jul 14, 2024 Pending
Array ( [id] => 20395022 [patent_doc_number] => 20250370497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => CHIPLET CLOCK FORWARDING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/680368 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680368
CHIPLET CLOCK FORWARDING ARCHITECTURE May 30, 2024 Pending
Array ( [id] => 19602945 [patent_doc_number] => 20240393825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Chip-to-Chip Flit Rate Synchronization [patent_app_type] => utility [patent_app_number] => 18/670213 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670213
Chip-to-Chip Flit Rate Synchronization May 20, 2024 Pending
Array ( [id] => 20365648 [patent_doc_number] => 20250355460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MULTI-PHASE CLOCK CALIBRATION IN A RECEIVER [patent_app_type] => utility [patent_app_number] => 18/667840 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667840
Multi-phase clock calibration in a receiver May 16, 2024 Issued
Array ( [id] => 19617075 [patent_doc_number] => 20240402755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => POWER MANAGEMENT BASED ON SELF-SYNCHRONIZATION OF CLOCKS [patent_app_type] => utility [patent_app_number] => 18/653846 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653846
POWER MANAGEMENT BASED ON SELF-SYNCHRONIZATION OF CLOCKS May 1, 2024 Pending
Array ( [id] => 20659194 [patent_doc_number] => 20260111237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => Method and Apparatus for Automatic Switching Between primary BIOS and backup BIOS, and Computer [patent_app_type] => utility [patent_app_number] => 19/147065 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19147065 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/147065
Method and Apparatus for Automatic Switching Between primary BIOS and backup BIOS, and Computer Apr 24, 2024 Pending
Array ( [id] => 20249564 [patent_doc_number] => 20250298433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => CLOCK AND DATA RECOVERY CIRCUIT MODULE, MEMORY STORAGE DEVICE AND SIGNAL CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 18/637397 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637397
Clock and data recovery circuit module, memory storage device and signal calibration method Apr 15, 2024 Issued
Array ( [id] => 19405416 [patent_doc_number] => 20240288927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DYNAMICALLY POWER ON/OFF PROCESSING CLUSTERS DURING EXECUTION [patent_app_type] => utility [patent_app_number] => 18/633932 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633932
DYNAMICALLY POWER ON/OFF PROCESSING CLUSTERS DURING EXECUTION Apr 11, 2024 Pending
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