| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05327579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Scanning systems using tree structures'
[patent_app_type] => 1
[patent_app_number] => 8/153276
[patent_app_country] => US
[patent_app_date] => 1993-11-16
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[firstpage_image] =>[orig_patent_app_number] => 153276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/153276 | Scanning systems using tree structures | Nov 15, 1993 | Issued |
Array
(
[id] => 3024467
[patent_doc_number] => 05276853
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'Cache system'
[patent_app_type] => 1
[patent_app_number] => 8/047386
[patent_app_country] => US
[patent_app_date] => 1993-04-16
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[pdf_file] => patents/05/276/05276853.pdf
[firstpage_image] =>[orig_patent_app_number] => 047386
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/047386 | Cache system | Apr 15, 1993 | Issued |
Array
(
[id] => 2952121
[patent_doc_number] => 05261109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Distributed arbitration method and apparatus for a computer bus using arbitration groups'
[patent_app_type] => 1
[patent_app_number] => 8/006138
[patent_app_country] => US
[patent_app_date] => 1993-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => patents/05/261/05261109.pdf
[firstpage_image] =>[orig_patent_app_number] => 006138
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/006138 | Distributed arbitration method and apparatus for a computer bus using arbitration groups | Jan 18, 1993 | Issued |
Array
(
[id] => 2934380
[patent_doc_number] => 05235697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Set prediction cache memory system using bits of the main memory address'
[patent_app_type] => 1
[patent_app_number] => 7/956827
[patent_app_country] => US
[patent_app_date] => 1992-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6950
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[pdf_file] => patents/05/235/05235697.pdf
[firstpage_image] =>[orig_patent_app_number] => 956827
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/956827 | Set prediction cache memory system using bits of the main memory address | Oct 4, 1992 | Issued |
| 07/955226 | COMPUTER PROGRAM ANALYZER FOR ADAPTING COMPUTER PROGRAMS TO DIFFERENT ARCHITECTURES | Sep 30, 1992 | Abandoned |
Array
(
[id] => 2925578
[patent_doc_number] => 05237686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-17
[patent_title] => 'Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority'
[patent_app_type] => 1
[patent_app_number] => 7/944404
[patent_app_country] => US
[patent_app_date] => 1992-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[pdf_file] => patents/05/237/05237686.pdf
[firstpage_image] =>[orig_patent_app_number] => 944404
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/944404 | Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority | Sep 13, 1992 | Issued |
| 07/920813 | DOCUMENT ANNOTATION AND MANIPULATION IN A DATA PROCESSING SYSTEM | Jul 23, 1992 | Abandoned |
| 07/908533 | IMPROVED POWER MANAGEMENT FOR DATA PROCESSING SYSTEM | Jun 28, 1992 | Abandoned |
Array
(
[id] => 2980234
[patent_doc_number] => 05202979
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Storage system using multiple independently mechanically-driven storage units'
[patent_app_type] => 1
[patent_app_number] => 7/906006
[patent_app_country] => US
[patent_app_date] => 1992-06-26
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[pdf_file] => patents/05/202/05202979.pdf
[firstpage_image] =>[orig_patent_app_number] => 906006
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/906006 | Storage system using multiple independently mechanically-driven storage units | Jun 25, 1992 | Issued |
Array
(
[id] => 2930433
[patent_doc_number] => 05193187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-09
[patent_title] => 'Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers'
[patent_app_type] => 1
[patent_app_number] => 7/898387
[patent_app_country] => US
[patent_app_date] => 1992-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/193/05193187.pdf
[firstpage_image] =>[orig_patent_app_number] => 898387
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/898387 | Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers | Jun 9, 1992 | Issued |
Array
(
[id] => 3041530
[patent_doc_number] => 05317700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Program history for pipelined processor including temporary storage queues for storing branch addresses'
[patent_app_type] => 1
[patent_app_number] => 7/877508
[patent_app_country] => US
[patent_app_date] => 1992-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2953
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317700.pdf
[firstpage_image] =>[orig_patent_app_number] => 877508
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/877508 | Program history for pipelined processor including temporary storage queues for storing branch addresses | Apr 30, 1992 | Issued |
| 07/876807 | APPARATUS FOR CONTROLLING A SIGNAL PROCESSING SYSTEM TO OPERATE IN HIGH AND LOW SPEED MODES | Apr 29, 1992 | Abandoned |
Array
(
[id] => 2901074
[patent_doc_number] => 05210639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Dual-port memory with inhibited random access during transfer cycles with serial access'
[patent_app_type] => 1
[patent_app_number] => 7/870721
[patent_app_country] => US
[patent_app_date] => 1992-04-10
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[pdf_file] => patents/05/210/05210639.pdf
[firstpage_image] =>[orig_patent_app_number] => 870721
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/870721 | Dual-port memory with inhibited random access during transfer cycles with serial access | Apr 9, 1992 | Issued |
Array
(
[id] => 2819764
[patent_doc_number] => 05157769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Computer data interface for handheld computer transfer to second computer including cable connector circuitry for voltage modification'
[patent_app_type] => 1
[patent_app_number] => 7/860293
[patent_app_country] => US
[patent_app_date] => 1992-03-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/157/05157769.pdf
[firstpage_image] =>[orig_patent_app_number] => 860293
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/860293 | Computer data interface for handheld computer transfer to second computer including cable connector circuitry for voltage modification | Mar 25, 1992 | Issued |
Array
(
[id] => 2872666
[patent_doc_number] => 05167024
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-24
[patent_title] => 'Power management for a laptop computer with slow and sleep modes'
[patent_app_type] => 1
[patent_app_number] => 7/845781
[patent_app_country] => US
[patent_app_date] => 1992-03-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/167/05167024.pdf
[firstpage_image] =>[orig_patent_app_number] => 845781
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/845781 | Power management for a laptop computer with slow and sleep modes | Mar 4, 1992 | Issued |
Array
(
[id] => 2924929
[patent_doc_number] => 05228139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-13
[patent_title] => 'Semiconductor integrated circuit device with test mode for testing CPU using external signal'
[patent_app_type] => 1
[patent_app_number] => 7/840633
[patent_app_country] => US
[patent_app_date] => 1992-02-21
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[firstpage_image] =>[orig_patent_app_number] => 840633
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/840633 | Semiconductor integrated circuit device with test mode for testing CPU using external signal | Feb 20, 1992 | Issued |
Array
(
[id] => 2797647
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'FIP-compliant block multiplexor channel interface operational method for cache/disk subsystem'
[patent_app_type] => 1
[patent_app_number] => 7/830963
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[firstpage_image] =>[orig_patent_app_number] => 830963
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830963 | FIP-compliant block multiplexor channel interface operational method for cache/disk subsystem | Feb 4, 1992 | Issued |
Array
(
[id] => 2832380
[patent_doc_number] => 05168566
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-01
[patent_title] => 'Multi-task control device for central processor task execution control provided as a peripheral device and capable of prioritizing and timesharing the tasks'
[patent_app_type] => 1
[patent_app_number] => 7/825334
[patent_app_country] => US
[patent_app_date] => 1992-01-27
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[pdf_file] => patents/05/168/05168566.pdf
[firstpage_image] =>[orig_patent_app_number] => 825334
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/825334 | Multi-task control device for central processor task execution control provided as a peripheral device and capable of prioritizing and timesharing the tasks | Jan 26, 1992 | Issued |
Array
(
[id] => 2835825
[patent_doc_number] => 05170471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-08
[patent_title] => 'Command delivery for a computing system for transferring data between a host and subsystems with busy and reset indication'
[patent_app_type] => 1
[patent_app_number] => 7/818654
[patent_app_country] => US
[patent_app_date] => 1992-01-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/170/05170471.pdf
[firstpage_image] =>[orig_patent_app_number] => 818654
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/818654 | Command delivery for a computing system for transferring data between a host and subsystems with busy and reset indication | Jan 5, 1992 | Issued |
| 07/793291 | CONTROL DEVICE FOR IMAGE FORMING APPARATUS | Nov 13, 1991 | Abandoned |