| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 04866668
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'Multiple memory loading system based on multilevel lists'
[patent_app_type] => 1
[patent_app_number] => 7/178887
[patent_app_country] => US
[patent_app_date] => 1988-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/178887 | Multiple memory loading system based on multilevel lists | Mar 29, 1988 | Issued |
| 07/175312 | MICROPROGRAM PROCESSOR | Mar 29, 1988 | Abandoned |
| 07/175077 | CONCURRENT SORTING APPARATUS AND METHOD | Mar 29, 1988 | Abandoned |
Array
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[id] => 2598020
[patent_doc_number] => 04959780
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Microprogram processor with logic circuitry for combining signals from a microcode decoder and an instruction code decoder to produce a memory access signal'
[patent_app_type] => 1
[patent_app_number] => 7/175293
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[pdf_file] => patents/04/959/04959780.pdf
[firstpage_image] =>[orig_patent_app_number] => 175293
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/175293 | Microprogram processor with logic circuitry for combining signals from a microcode decoder and an instruction code decoder to produce a memory access signal | Mar 29, 1988 | Issued |
Array
(
[id] => 2697340
[patent_doc_number] => 05050074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'System for facilitating coordination of activities by a plurality of actors with an object database and state/action identification'
[patent_app_type] => 1
[patent_app_number] => 7/173768
[patent_app_country] => US
[patent_app_date] => 1988-03-28
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[firstpage_image] =>[orig_patent_app_number] => 173768
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/173768 | System for facilitating coordination of activities by a plurality of actors with an object database and state/action identification | Mar 27, 1988 | Issued |
Array
(
[id] => 2560759
[patent_doc_number] => 04833596
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-23
[patent_title] => 'Logical arrangement for controlling use of different system displays by main processor and co-processor'
[patent_app_type] => 1
[patent_app_number] => 7/172042
[patent_app_country] => US
[patent_app_date] => 1988-03-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 172042
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/172042 | Logical arrangement for controlling use of different system displays by main processor and co-processor | Mar 22, 1988 | Issued |
| 07/171624 | DATA PROCESSOR FOR INVALIDATING PREFETCHED INSTRUCTION OR BRANCH HISTORY INFORMATION | Mar 21, 1988 | Abandoned |
Array
(
[id] => 2493600
[patent_doc_number] => 04866605
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-12
[patent_title] => 'System function simulation method and apparatus therefor using Petri net symbols'
[patent_app_type] => 1
[patent_app_number] => 7/172980
[patent_app_country] => US
[patent_app_date] => 1988-03-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/172980 | System function simulation method and apparatus therefor using Petri net symbols | Mar 21, 1988 | Issued |
| 07/167748 | RECORD LOCK PROCESSING FOR MULTIPROCESSING DATA SYSTEM | Mar 13, 1988 | Abandoned |
| 07/166560 | COMPUTER SYSTEM | Mar 8, 1988 | Abandoned |
| 07/163980 | TIMED ACCESS SYSTEM FOR PROTECTING DATA IN A CENTRAL PROCESSING UNIT | Mar 3, 1988 | Abandoned |
Array
(
[id] => 2588506
[patent_doc_number] => 04974153
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-27
[patent_title] => 'Repeater interlock scheme for transactions between two buses including transaction and interlock buffers'
[patent_app_type] => 1
[patent_app_number] => 7/162620
[patent_app_country] => US
[patent_app_date] => 1988-03-01
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[pdf_file] => patents/04/974/04974153.pdf
[firstpage_image] =>[orig_patent_app_number] => 162620
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/162620 | Repeater interlock scheme for transactions between two buses including transaction and interlock buffers | Feb 29, 1988 | Issued |
Array
(
[id] => 2636802
[patent_doc_number] => 04907148
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Cellular array processor with individual cell-level data-dependent cell control and multiport input memory'
[patent_app_type] => 1
[patent_app_number] => 7/163177
[patent_app_country] => US
[patent_app_date] => 1988-02-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/907/04907148.pdf
[firstpage_image] =>[orig_patent_app_number] => 163177
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/163177 | Cellular array processor with individual cell-level data-dependent cell control and multiport input memory | Feb 25, 1988 | Issued |
Array
(
[id] => 2500742
[patent_doc_number] => 04860248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-22
[patent_title] => 'Pixel slice processor with frame buffers grouped according to pixel bit width'
[patent_app_type] => 1
[patent_app_number] => 7/163160
[patent_app_country] => US
[patent_app_date] => 1988-02-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/860/04860248.pdf
[firstpage_image] =>[orig_patent_app_number] => 163160
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/163160 | Pixel slice processor with frame buffers grouped according to pixel bit width | Feb 24, 1988 | Issued |
| 07/159222 | LOGICAL CACHE MEMORY FOR MULTI-PROCESSOR SYSTEM | Feb 22, 1988 | Abandoned |
| 07/161232 | CONTROL CIRCUIT FOR AUTONOMOUS COUNTERS OF A PLURALITY OF CPU'S OR THE LIKE | Feb 16, 1988 | Abandoned |
| 07/154641 | STATE MACHINE BUS CONTROLLER | Feb 8, 1988 | Abandoned |
Array
(
[id] => 2676746
[patent_doc_number] => 04905139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-27
[patent_title] => 'Cache memory system with improved re-writing address determination scheme involving history of use'
[patent_app_type] => 1
[patent_app_number] => 7/153891
[patent_app_country] => US
[patent_app_date] => 1988-02-09
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 153891
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/153891 | Cache memory system with improved re-writing address determination scheme involving history of use | Feb 8, 1988 | Issued |
Array
(
[id] => 2422075
[patent_doc_number] => 04787065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-11-22
[patent_title] => 'Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions'
[patent_app_type] => 1
[patent_app_number] => 7/153526
[patent_app_country] => US
[patent_app_date] => 1988-02-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/787/04787065.pdf
[firstpage_image] =>[orig_patent_app_number] => 153526
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/153526 | Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions | Feb 2, 1988 | Issued |
| 07/149421 | FILE INDEX SYSTEM FOR MASS STORAGE DEVICE | Jan 28, 1988 | Abandoned |