Lawrence E. Anderson

Array ( [id] => 2392444 [patent_doc_number] => 04709326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-11-24 [patent_title] => 'General locking/synchronization facility with canonical states and mapping of processors' [patent_app_type] => 1 [patent_app_number] => 6/626163 [patent_app_country] => US [patent_app_date] => 1984-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4977 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/709/04709326.pdf [firstpage_image] =>[orig_patent_app_number] => 626163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2330745 [patent_doc_number] => 04680703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-14 [patent_title] => 'Data processing system with reorganization of disk storage for improved paging' [patent_app_type] => 1 [patent_app_number] => 6/624485 [patent_app_country] => US [patent_app_date] => 1984-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4877 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/680/04680703.pdf [firstpage_image] =>[orig_patent_app_number] => 624485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2331681 [patent_doc_number] => 04636978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-01-13 [patent_title] => 'Programmable status register arrangement' [patent_app_type] => 1 [patent_app_number] => 6/620197 [patent_app_country] => US [patent_app_date] => 1984-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1198 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/636/04636978.pdf [firstpage_image] =>[orig_patent_app_number] => 620197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2334586 [patent_doc_number] => 04672534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-09 [patent_title] => 'Integrated circuit device incorporating a data processing unit and a ROM storing applications program therein' [patent_app_type] => 1 [patent_app_number] => 6/611999 [patent_app_country] => US [patent_app_date] => 1984-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1817 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 728 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/672/04672534.pdf [firstpage_image] =>[orig_patent_app_number] => 611999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2324571 [patent_doc_number] => 04689741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-25 [patent_title] => 'Video system having a dual-port memory with inhibited random access during transfer cycles' [patent_app_type] => 1 [patent_app_number] => 6/567039 [patent_app_country] => US [patent_app_date] => 1983-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 10058 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/689/04689741.pdf [firstpage_image] =>[orig_patent_app_number] => 567039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2635635 [patent_doc_number] => 04967343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-30 [patent_title] => 'Pipelined parallel vector processor including parallel configured element processors for processing vector elements in parallel fashion' [patent_app_type] => 1 [patent_app_number] => 6/530842 [patent_app_country] => US [patent_app_date] => 1983-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3909 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/967/04967343.pdf [firstpage_image] =>[orig_patent_app_number] => 530842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2322377 [patent_doc_number] => 04686621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-11 [patent_title] => 'Test apparatus for testing a multilevel cache system with graceful degradation capability' [patent_app_type] => 1 [patent_app_number] => 6/510079 [patent_app_country] => US [patent_app_date] => 1983-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 13624 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/686/04686621.pdf [firstpage_image] =>[orig_patent_app_number] => 510079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2364732 [patent_doc_number] => 04667288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-05-19 [patent_title] => 'Enable/disable control checking apparatus' [patent_app_type] => 1 [patent_app_number] => 6/509898 [patent_app_country] => US [patent_app_date] => 1983-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 11 [patent_no_of_words] => 13298 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/667/04667288.pdf [firstpage_image] =>[orig_patent_app_number] => 509898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2667023 [patent_doc_number] => 04979095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-18 [patent_title] => 'Apparatus and method for a data processing system interface having multiple bit protocol signals' [patent_app_type] => 1 [patent_app_number] => 6/499215 [patent_app_country] => US [patent_app_date] => 1983-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 8092 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/979/04979095.pdf [firstpage_image] =>[orig_patent_app_number] => 499215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2183816 [patent_doc_number] => 04513373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-04-23 [patent_title] => 'Local area network' [patent_app_type] => 1 [patent_app_number] => 6/454054 [patent_app_country] => US [patent_app_date] => 1982-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1723 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/513/04513373.pdf [firstpage_image] =>[orig_patent_app_number] => 454054 [rel_patent_id] =>[rel_patent_doc_number] =>)