Search

Lawrence E. Anderson

Examiner (ID: 12344)

Most Active Art Unit
2301
Art Unit(s)
2308, 2301, 2302
Total Applications
332
Issued Applications
188
Pending Applications
0
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2717449 [patent_doc_number] => 05056006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Parallel processor with single program storage and sequencer and simultaneous instruction processing' [patent_app_type] => 1 [patent_app_number] => 7/551682 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4935 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/056/05056006.pdf [firstpage_image] =>[orig_patent_app_number] => 551682 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/551682
Parallel processor with single program storage and sequencer and simultaneous instruction processing Jul 8, 1990 Issued
07/549329 STRUCTURE FOR ENABLING DIRECT MEMORY-TO-MEMORY TRANSFER Jul 5, 1990 Abandoned
07/546509 SET PREDICTION CACHE MEMORY SYSTEM Jun 28, 1990 Abandoned
Array ( [id] => 2908556 [patent_doc_number] => 05241679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register' [patent_app_type] => 1 [patent_app_number] => 7/545290 [patent_app_country] => US [patent_app_date] => 1990-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4106 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241679.pdf [firstpage_image] =>[orig_patent_app_number] => 545290 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/545290
Data processor for executing data saving and restoration register and data saving stack with corresponding stack storage for each register Jun 26, 1990 Issued
Array ( [id] => 2804046 [patent_doc_number] => 05136710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Dynamic inactivation of program exits of the application program while the system program is running' [patent_app_type] => 1 [patent_app_number] => 7/541429 [patent_app_country] => US [patent_app_date] => 1990-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2412 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136710.pdf [firstpage_image] =>[orig_patent_app_number] => 541429 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/541429
Dynamic inactivation of program exits of the application program while the system program is running Jun 20, 1990 Issued
07/536199 FAST INTERRUPT MECHANISM FOR A MULTIPROCESSOR SYSTEM Jun 10, 1990 Abandoned
Array ( [id] => 2812933 [patent_doc_number] => 05140692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Document retrieval system using analog signal comparisons for retrieval conditions including relevant keywords' [patent_app_type] => 1 [patent_app_number] => 7/533829 [patent_app_country] => US [patent_app_date] => 1990-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2329 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140692.pdf [firstpage_image] =>[orig_patent_app_number] => 533829 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/533829
Document retrieval system using analog signal comparisons for retrieval conditions including relevant keywords Jun 5, 1990 Issued
07/534297 DUAL-PORT MEMORY WITH INHIBITED RANDOM ACCESS DURING TRANSFER CYCLES Jun 4, 1990 Abandoned
07/532314 POWER MANAGEMENT FOR DATA PROCESSING SYSTEM May 31, 1990 Abandoned
Array ( [id] => 2930825 [patent_doc_number] => 05193207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Link sorted memory' [patent_app_type] => 1 [patent_app_number] => 7/531199 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3272 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193207.pdf [firstpage_image] =>[orig_patent_app_number] => 531199 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/531199
Link sorted memory May 30, 1990 Issued
Array ( [id] => 2925118 [patent_doc_number] => 05237661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Buffer management method and system therefor using an I/O buffer on main memory and utilizing virtual memory and page fixing' [patent_app_type] => 1 [patent_app_number] => 7/530026 [patent_app_country] => US [patent_app_date] => 1990-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 20531 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237661.pdf [firstpage_image] =>[orig_patent_app_number] => 530026 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/530026
Buffer management method and system therefor using an I/O buffer on main memory and utilizing virtual memory and page fixing May 28, 1990 Issued
07/527059 EXTENDED MODE ANALYZER FOR ASSISTING IN ADAPTING COMPUTER CODE TO DIFFERENT ARCHITECTURES May 22, 1990 Abandoned
07/524706 METHOD AND APPARATUS FOR CONTROLLING POWER TO DEVICES IN A COMPUTER SYSTEM May 16, 1990 Abandoned
Array ( [id] => 2707597 [patent_doc_number] => 04989138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Single bus graphics data processing pipeline with decentralized bus arbitration' [patent_app_type] => 1 [patent_app_number] => 7/522508 [patent_app_country] => US [patent_app_date] => 1990-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 13027 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/989/04989138.pdf [firstpage_image] =>[orig_patent_app_number] => 522508 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/522508
Single bus graphics data processing pipeline with decentralized bus arbitration May 13, 1990 Issued
Array ( [id] => 2775716 [patent_doc_number] => 05007020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Method for memory addressing and control with reversal of higher and lower address' [patent_app_type] => 1 [patent_app_number] => 7/519839 [patent_app_country] => US [patent_app_date] => 1990-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7423 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/007/05007020.pdf [firstpage_image] =>[orig_patent_app_number] => 519839 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/519839
Method for memory addressing and control with reversal of higher and lower address May 6, 1990 Issued
Array ( [id] => 2724358 [patent_doc_number] => 05053946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Token ring network having token request mechanism' [patent_app_type] => 1 [patent_app_number] => 7/519313 [patent_app_country] => US [patent_app_date] => 1990-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3900 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053946.pdf [firstpage_image] =>[orig_patent_app_number] => 519313 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/519313
Token ring network having token request mechanism May 6, 1990 Issued
07/518232 CONTROL DEVICE FOR IMAGE FORMING APPARATUS May 6, 1990 Abandoned
Array ( [id] => 2888259 [patent_doc_number] => 05119291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Modular data storage directories for large-capacity data storage units wherein the index to the records in a sector is located in the next adjacent sector' [patent_app_type] => 1 [patent_app_number] => 7/517287 [patent_app_country] => US [patent_app_date] => 1990-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 18616 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119291.pdf [firstpage_image] =>[orig_patent_app_number] => 517287 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/517287
Modular data storage directories for large-capacity data storage units wherein the index to the records in a sector is located in the next adjacent sector Apr 30, 1990 Issued
Array ( [id] => 2741589 [patent_doc_number] => 05040108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'Information processing system having microprogram-controlled type arithmetic processing unit with clock synchronization instruction' [patent_app_type] => 1 [patent_app_number] => 7/513228 [patent_app_country] => US [patent_app_date] => 1990-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2627 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/040/05040108.pdf [firstpage_image] =>[orig_patent_app_number] => 513228 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/513228
Information processing system having microprogram-controlled type arithmetic processing unit with clock synchronization instruction Apr 22, 1990 Issued
Array ( [id] => 2715153 [patent_doc_number] => 04992938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers' [patent_app_type] => 1 [patent_app_number] => 7/469813 [patent_app_country] => US [patent_app_date] => 1990-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8942 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992938.pdf [firstpage_image] =>[orig_patent_app_number] => 469813 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/469813
Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers Apr 22, 1990 Issued
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