Search

Lawrence E. Anderson

Examiner (ID: 12344)

Most Active Art Unit
2301
Art Unit(s)
2308, 2301, 2302
Total Applications
332
Issued Applications
188
Pending Applications
0
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2927531 [patent_doc_number] => 05179670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Slot determination mechanism using pulse counting' [patent_app_type] => 1 [patent_app_number] => 7/444633 [patent_app_country] => US [patent_app_date] => 1989-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3482 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179670.pdf [firstpage_image] =>[orig_patent_app_number] => 444633 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/444633
Slot determination mechanism using pulse counting Nov 30, 1989 Issued
Array ( [id] => 2718195 [patent_doc_number] => 04982432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Electrotactile vocoder' [patent_app_type] => 1 [patent_app_number] => 7/443857 [patent_app_country] => US [patent_app_date] => 1989-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 4 [patent_no_of_words] => 3515 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/982/04982432.pdf [firstpage_image] =>[orig_patent_app_number] => 443857 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/443857
Electrotactile vocoder Nov 28, 1989 Issued
Array ( [id] => 2724303 [patent_doc_number] => 05053943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'Control circuit for autonomous counters of a plurality of CPU\'s or the like with intermittent operation and reset after a predetermined count' [patent_app_type] => 1 [patent_app_number] => 7/443032 [patent_app_country] => US [patent_app_date] => 1989-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2477 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053943.pdf [firstpage_image] =>[orig_patent_app_number] => 443032 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/443032
Control circuit for autonomous counters of a plurality of CPU's or the like with intermittent operation and reset after a predetermined count Nov 27, 1989 Issued
Array ( [id] => 2961707 [patent_doc_number] => 05222230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges' [patent_app_type] => 1 [patent_app_number] => 7/439966 [patent_app_country] => US [patent_app_date] => 1989-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/222/05222230.pdf [firstpage_image] =>[orig_patent_app_number] => 439966 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/439966
Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges Nov 19, 1989 Issued
Array ( [id] => 2927436 [patent_doc_number] => 05179665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory' [patent_app_type] => 1 [patent_app_number] => 7/436112 [patent_app_country] => US [patent_app_date] => 1989-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 38 [patent_no_of_words] => 8821 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179665.pdf [firstpage_image] =>[orig_patent_app_number] => 436112 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/436112
Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory Nov 12, 1989 Issued
07/431709 STORAGE SYSTEM USING MULTIPLE MECHANICALLY-DRIVEN STORAGE UNITS Nov 1, 1989 Abandoned
07/427692 DOCUMENT ANNOTATION AND MANIPULATION IN A DATA PROCESSING SYSTEM Oct 26, 1989 Abandoned
07/418995 DATA TRANSFER SYSTEM Oct 9, 1989 Abandoned
Array ( [id] => 2775721 [patent_doc_number] => 05036456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Apparatus for controlling concurrent operations of a system control unit including activity register circuitry' [patent_app_type] => 1 [patent_app_number] => 7/409982 [patent_app_country] => US [patent_app_date] => 1989-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11534 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036456.pdf [firstpage_image] =>[orig_patent_app_number] => 409982 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/409982
Apparatus for controlling concurrent operations of a system control unit including activity register circuitry Sep 18, 1989 Issued
Array ( [id] => 2741575 [patent_doc_number] => 05032983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'Entry point mapping and skipping method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/409978 [patent_app_country] => US [patent_app_date] => 1989-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2260 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/032/05032983.pdf [firstpage_image] =>[orig_patent_app_number] => 409978 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/409978
Entry point mapping and skipping method and apparatus Sep 17, 1989 Issued
07/405637 POWER MANAGEMENT FOR A LAPTOP COMPUTER Sep 7, 1989 Abandoned
07/395910 FIXED DISK DRIVE DATA STORAGE MODULE Aug 17, 1989 Abandoned
07/396739 DOCUMENT ANNOTATION & MANIPULATION IN A DATA PROCESSING SYSTEM Aug 17, 1989 Abandoned
07/388304 SOFTWARE PROGRAMMABLE LOGIC ARRAY Jul 26, 1989 Abandoned
07/383215 COMPUTER DATA INTERFACE Jul 20, 1989 Abandoned
Array ( [id] => 2678704 [patent_doc_number] => 05047919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Method and apparatus for monitoring software execution in a parallel multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 7/382063 [patent_app_country] => US [patent_app_date] => 1989-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7614 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047919.pdf [firstpage_image] =>[orig_patent_app_number] => 382063 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/382063
Method and apparatus for monitoring software execution in a parallel multiprocessor computer system Jul 13, 1989 Issued
07/373216 INPUT/OUTPUT EXECUTION APPARATUS FOR A PLURAL-OS RUN SYSTEM Jun 27, 1989 Abandoned
Array ( [id] => 2714962 [patent_doc_number] => 05068785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Bus control for small computer system interface with transfer indication preceding final word transfer and buffer empty indication preceding receipt acknowledgement' [patent_app_type] => 1 [patent_app_number] => 7/367635 [patent_app_country] => US [patent_app_date] => 1989-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5972 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068785.pdf [firstpage_image] =>[orig_patent_app_number] => 367635 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/367635
Bus control for small computer system interface with transfer indication preceding final word transfer and buffer empty indication preceding receipt acknowledgement Jun 18, 1989 Issued
Array ( [id] => 2888655 [patent_doc_number] => 05185864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Interrupt handling for a computing system with logical devices and interrupt reset' [patent_app_type] => 1 [patent_app_number] => 7/367391 [patent_app_country] => US [patent_app_date] => 1989-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 42 [patent_no_of_words] => 25525 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185864.pdf [firstpage_image] =>[orig_patent_app_number] => 367391 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/367391
Interrupt handling for a computing system with logical devices and interrupt reset Jun 15, 1989 Issued
Array ( [id] => 2704906 [patent_doc_number] => 04991081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-05 [patent_title] => 'Cache memory addressable by both physical and virtual addresses' [patent_app_type] => 1 [patent_app_number] => 7/368140 [patent_app_country] => US [patent_app_date] => 1989-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7396 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/991/04991081.pdf [firstpage_image] =>[orig_patent_app_number] => 368140 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/368140
Cache memory addressable by both physical and virtual addresses Jun 15, 1989 Issued
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