Lee D Wilson
Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )
Most Active Art Unit | 3723 |
Art Unit(s) | 3203, 3723, 3727 |
Total Applications | 4059 |
Issued Applications | 3286 |
Pending Applications | 170 |
Abandoned Applications | 602 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3116834
[patent_doc_number] => 05418737
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'DRAM with sub data lines and match lines for test'
[patent_app_type] => 1
[patent_app_number] => 8/246913
[patent_app_country] => US
[patent_app_date] => 1994-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4831
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/418/05418737.pdf
[firstpage_image] =>[orig_patent_app_number] => 246913
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/246913 | DRAM with sub data lines and match lines for test | May 19, 1994 | Issued |
Array
(
[id] => 3498871
[patent_doc_number] => 05471423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/243621
[patent_app_country] => US
[patent_app_date] => 1994-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 6718
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471423.pdf
[firstpage_image] =>[orig_patent_app_number] => 243621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/243621 | Non-volatile semiconductor memory device | May 15, 1994 | Issued |
Array
(
[id] => 3418259
[patent_doc_number] => 05438551
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/243584
[patent_app_country] => US
[patent_app_date] => 1994-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7268
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438551.pdf
[firstpage_image] =>[orig_patent_app_number] => 243584
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/243584 | Semiconductor integrated circuit device | May 15, 1994 | Issued |
Array
(
[id] => 3623262
[patent_doc_number] => 05535156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same'
[patent_app_type] => 1
[patent_app_number] => 8/238390
[patent_app_country] => US
[patent_app_date] => 1994-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 23
[patent_no_of_words] => 8500
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/535/05535156.pdf
[firstpage_image] =>[orig_patent_app_number] => 238390
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/238390 | Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same | May 4, 1994 | Issued |
Array
(
[id] => 3452399
[patent_doc_number] => 05467315
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Semiconductor memory device facilitated with plural self-refresh modes'
[patent_app_type] => 1
[patent_app_number] => 8/234414
[patent_app_country] => US
[patent_app_date] => 1994-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 68
[patent_no_of_words] => 27220
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467315.pdf
[firstpage_image] =>[orig_patent_app_number] => 234414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/234414 | Semiconductor memory device facilitated with plural self-refresh modes | Apr 27, 1994 | Issued |
Array
(
[id] => 3495319
[patent_doc_number] => 05426615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-20
[patent_title] => 'Semiconductor memory device having power line arranged in a meshed shape'
[patent_app_type] => 1
[patent_app_number] => 8/224461
[patent_app_country] => US
[patent_app_date] => 1994-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 12725
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/426/05426615.pdf
[firstpage_image] =>[orig_patent_app_number] => 224461
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/224461 | Semiconductor memory device having power line arranged in a meshed shape | Apr 6, 1994 | Issued |
Array
(
[id] => 3128885
[patent_doc_number] => 05450357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-12
[patent_title] => 'Level shifter circuit'
[patent_app_type] => 1
[patent_app_number] => 8/221730
[patent_app_country] => US
[patent_app_date] => 1994-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4141
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/450/05450357.pdf
[firstpage_image] =>[orig_patent_app_number] => 221730
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/221730 | Level shifter circuit | Mar 31, 1994 | Issued |
08/218740 | METHOD OF DRIVING FERROELECTRIC GATE TRANSISTOR MEMORY CELL | Mar 27, 1994 | Abandoned |
Array
(
[id] => 3122760
[patent_doc_number] => 05414656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Low charge consumption memory'
[patent_app_type] => 1
[patent_app_number] => 8/216611
[patent_app_country] => US
[patent_app_date] => 1994-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 42
[patent_no_of_words] => 3615
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/414/05414656.pdf
[firstpage_image] =>[orig_patent_app_number] => 216611
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/216611 | Low charge consumption memory | Mar 22, 1994 | Issued |
Array
(
[id] => 3130784
[patent_doc_number] => 05384730
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-24
[patent_title] => 'Coincident activation of pass transistors in a random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/216776
[patent_app_country] => US
[patent_app_date] => 1994-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 42
[patent_no_of_words] => 19489
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/384/05384730.pdf
[firstpage_image] =>[orig_patent_app_number] => 216776
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/216776 | Coincident activation of pass transistors in a random access memory | Mar 22, 1994 | Issued |
08/215461 | SRAM CELL USING WORD LINE CONTROLLED PULL-UP NMOS TRANSISTORS | Mar 20, 1994 | Abandoned |
Array
(
[id] => 3504803
[patent_doc_number] => 05508963
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/209120
[patent_app_country] => US
[patent_app_date] => 1994-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 69
[patent_no_of_words] => 24448
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/508/05508963.pdf
[firstpage_image] =>[orig_patent_app_number] => 209120
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/209120 | Semiconductor integrated circuit | Mar 10, 1994 | Issued |
Array
(
[id] => 3432995
[patent_doc_number] => 05422851
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Semiconductor memory device capable of verifying use of redundant circuit'
[patent_app_type] => 1
[patent_app_number] => 8/208210
[patent_app_country] => US
[patent_app_date] => 1994-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5650
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/422/05422851.pdf
[firstpage_image] =>[orig_patent_app_number] => 208210
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/208210 | Semiconductor memory device capable of verifying use of redundant circuit | Mar 9, 1994 | Issued |
Array
(
[id] => 3012774
[patent_doc_number] => 05371713
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/207677
[patent_app_country] => US
[patent_app_date] => 1994-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 11414
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371713.pdf
[firstpage_image] =>[orig_patent_app_number] => 207677
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/207677 | Semiconductor integrated circuit | Mar 8, 1994 | Issued |
Array
(
[id] => 3499780
[patent_doc_number] => 05440514
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Write control for a memory using a delay locked loop'
[patent_app_type] => 1
[patent_app_number] => 8/207510
[patent_app_country] => US
[patent_app_date] => 1994-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 19634
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440514.pdf
[firstpage_image] =>[orig_patent_app_number] => 207510
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/207510 | Write control for a memory using a delay locked loop | Mar 7, 1994 | Issued |
Array
(
[id] => 3466839
[patent_doc_number] => 05402389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Synchronous memory having parallel output data paths'
[patent_app_type] => 1
[patent_app_number] => 8/207513
[patent_app_country] => US
[patent_app_date] => 1994-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 19845
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/402/05402389.pdf
[firstpage_image] =>[orig_patent_app_number] => 207513
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/207513 | Synchronous memory having parallel output data paths | Mar 7, 1994 | Issued |
Array
(
[id] => 3534527
[patent_doc_number] => 05504700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Method and apparatus for high density sixteen and thirty-two megabyte single in-line memory module'
[patent_app_type] => 1
[patent_app_number] => 8/199714
[patent_app_country] => US
[patent_app_date] => 1994-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2877
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 768
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504700.pdf
[firstpage_image] =>[orig_patent_app_number] => 199714
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/199714 | Method and apparatus for high density sixteen and thirty-two megabyte single in-line memory module | Feb 21, 1994 | Issued |
08/198631 | SEMICONDUCTOR MEMORY HAVING A REFRESH OPERATING CYCLE AND OPERATING AT A HIGH SPEED AND REDUCED POWER CONSUMPTION IN A NORMAL CYCLE | Feb 17, 1994 | Abandoned |
Array
(
[id] => 3489352
[patent_doc_number] => 05457655
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Column redundance circuit configuration for a memory'
[patent_app_type] => 1
[patent_app_number] => 8/198502
[patent_app_country] => US
[patent_app_date] => 1994-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 9251
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/457/05457655.pdf
[firstpage_image] =>[orig_patent_app_number] => 198502
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/198502 | Column redundance circuit configuration for a memory | Feb 16, 1994 | Issued |
Array
(
[id] => 3499694
[patent_doc_number] => 05440508
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Zero power high speed programmable circuit device architecture'
[patent_app_type] => 1
[patent_app_number] => 8/194930
[patent_app_country] => US
[patent_app_date] => 1994-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2974
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440508.pdf
[firstpage_image] =>[orig_patent_app_number] => 194930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/194930 | Zero power high speed programmable circuit device architecture | Feb 8, 1994 | Issued |