Lee D Wilson

Array ( [id] => 3822530 [patent_doc_number] => 05710740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM' [patent_app_type] => 1 [patent_app_number] => 8/717836 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3074 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710740.pdf [firstpage_image] =>[orig_patent_app_number] => 717836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892462 [patent_doc_number] => 05748540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Prevention of erroneous operation in equalizing operation in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/715642 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4204 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748540.pdf [firstpage_image] =>[orig_patent_app_number] => 715642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784040 [patent_doc_number] => 05774411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Methods to enhance SOI SRAM cell stability' [patent_app_type] => 1 [patent_app_number] => 8/712537 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774411.pdf [firstpage_image] =>[orig_patent_app_number] => 712537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784055 [patent_doc_number] => 05774412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Local word line phase driver' [patent_app_type] => 1 [patent_app_number] => 8/706647 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2786 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774412.pdf [firstpage_image] =>[orig_patent_app_number] => 706647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757046 [patent_doc_number] => 05717653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Late-write type SRAM in which address-decoding time for reading data differs from address-decoding time for writing data' [patent_app_type] => 1 [patent_app_number] => 8/708042 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717653.pdf [firstpage_image] =>[orig_patent_app_number] => 708042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697251 [patent_doc_number] => 05696722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Level-shifter, semiconductor integrated circuit, and control methods thereof' [patent_app_type] => 1 [patent_app_number] => 8/700940 [patent_app_country] => US [patent_app_date] => 1996-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 64 [patent_no_of_words] => 15146 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696722.pdf [firstpage_image] =>[orig_patent_app_number] => 700940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3912775 [patent_doc_number] => 05751628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Ferroelectric memory devices and method for testing them' [patent_app_type] => 1 [patent_app_number] => 8/700240 [patent_app_country] => US [patent_app_date] => 1996-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3532 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751628.pdf [firstpage_image] =>[orig_patent_app_number] => 700240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3798470 [patent_doc_number] => 05737263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Semiconductor memory of high integration, large capacity, and low power consumption' [patent_app_type] => 1 [patent_app_number] => 8/688740 [patent_app_country] => US [patent_app_date] => 1996-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3747 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737263.pdf [firstpage_image] =>[orig_patent_app_number] => 688740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3867177 [patent_doc_number] => 05768212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/688440 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2814 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768212.pdf [firstpage_image] =>[orig_patent_app_number] => 688440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3703373 [patent_doc_number] => 05650972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Semiconductor memory device having power line arranged in a meshed shape' [patent_app_type] => 1 [patent_app_number] => 8/692819 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12727 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650972.pdf [firstpage_image] =>[orig_patent_app_number] => 692819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3897651 [patent_doc_number] => 05715194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Bias scheme of program inhibit for random programming in a nand flash memory' [patent_app_type] => 1 [patent_app_number] => 8/686641 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4004 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715194.pdf [firstpage_image] =>[orig_patent_app_number] => 686641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3747462 [patent_doc_number] => 05699308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Semiconductor memory device having two layers of bit lines arranged crossing with each other' [patent_app_type] => 1 [patent_app_number] => 8/686626 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7362 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699308.pdf [firstpage_image] =>[orig_patent_app_number] => 686626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892350 [patent_doc_number] => 05748532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Semiconductor nonvolatile memory device and computer system using the same' [patent_app_type] => 1 [patent_app_number] => 8/677842 [patent_app_country] => US [patent_app_date] => 1996-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 39 [patent_no_of_words] => 12411 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748532.pdf [firstpage_image] =>[orig_patent_app_number] => 677842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756790 [patent_doc_number] => 05717637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/666238 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6501 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717637.pdf [firstpage_image] =>[orig_patent_app_number] => 666238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3900674 [patent_doc_number] => 05777923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Flash memory read/write controller' [patent_app_type] => 1 [patent_app_number] => 8/664639 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 9364 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777923.pdf [firstpage_image] =>[orig_patent_app_number] => 664639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3698024 [patent_doc_number] => 05691943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Page mode mask ROM using a two-stage latch circuit and a method for controlling the same' [patent_app_type] => 1 [patent_app_number] => 8/659837 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2659 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691943.pdf [firstpage_image] =>[orig_patent_app_number] => 659837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3789209 [patent_doc_number] => 05808942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Field programmable gate array (FPGA) having an improved configuration memory and look up table' [patent_app_type] => 1 [patent_app_number] => 8/659941 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2870 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808942.pdf [firstpage_image] =>[orig_patent_app_number] => 659941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3704252 [patent_doc_number] => 05680352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Circuit for generating a delayed standby signal in response to an external standby command' [patent_app_type] => 1 [patent_app_number] => 8/660204 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5888 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680352.pdf [firstpage_image] =>[orig_patent_app_number] => 660204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3804394 [patent_doc_number] => 05726930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/653236 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 12691 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726930.pdf [firstpage_image] =>[orig_patent_app_number] => 653236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3897911 [patent_doc_number] => 05715212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Semiconductor memory device comprising address transition detecting circuit having stable response characteristic for address signal conversion' [patent_app_type] => 1 [patent_app_number] => 8/652038 [patent_app_country] => US [patent_app_date] => 1996-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8646 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715212.pdf [firstpage_image] =>[orig_patent_app_number] => 652038 [rel_patent_id] =>[rel_patent_doc_number] =>)