Lee D Wilson

Array ( [id] => 3090726 [patent_doc_number] => 05321664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Semiconductor integrated circuit device having various blocks specifically arranged on a single semiconductor substrate for high speed operation' [patent_app_type] => 1 [patent_app_number] => 7/464032 [patent_app_country] => US [patent_app_date] => 1990-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6692 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321664.pdf [firstpage_image] =>[orig_patent_app_number] => 464032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2719441 [patent_doc_number] => 05018099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-21 [patent_title] => 'Comparison circuit' [patent_app_type] => 1 [patent_app_number] => 7/461901 [patent_app_country] => US [patent_app_date] => 1990-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3460 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/018/05018099.pdf [firstpage_image] =>[orig_patent_app_number] => 461901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2806799 [patent_doc_number] => 05144583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Dynamic semiconductor memory device with twisted bit-line structure' [patent_app_type] => 1 [patent_app_number] => 7/461121 [patent_app_country] => US [patent_app_date] => 1990-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 8386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144583.pdf [firstpage_image] =>[orig_patent_app_number] => 461121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2715998 [patent_doc_number] => 04992984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Memory module utilizing partially defective memory chips' [patent_app_type] => 1 [patent_app_number] => 7/458001 [patent_app_country] => US [patent_app_date] => 1989-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4919 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992984.pdf [firstpage_image] =>[orig_patent_app_number] => 458001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2688899 [patent_doc_number] => 05005156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-02 [patent_title] => 'Semiconductor device having output buffer circuit controlled by output control signal' [patent_app_type] => 1 [patent_app_number] => 7/457631 [patent_app_country] => US [patent_app_date] => 1989-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3370 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/005/05005156.pdf [firstpage_image] =>[orig_patent_app_number] => 457631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2881844 [patent_doc_number] => 05091889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Semiconductor memory having an operation margin against a write recovery time' [patent_app_type] => 1 [patent_app_number] => 7/456452 [patent_app_country] => US [patent_app_date] => 1989-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091889.pdf [firstpage_image] =>[orig_patent_app_number] => 456452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2863811 [patent_doc_number] => 05126971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Thin film magnetic core memory and method of making same' [patent_app_type] => 1 [patent_app_number] => 7/455070 [patent_app_country] => US [patent_app_date] => 1989-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4895 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126971.pdf [firstpage_image] =>[orig_patent_app_number] => 455070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2565138 [patent_doc_number] => 04961170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-02 [patent_title] => 'Logic circuit using bipolar complementary metal oxide semiconductor gate and semiconductor memory device having the logic circuit' [patent_app_type] => 1 [patent_app_number] => 7/452421 [patent_app_country] => US [patent_app_date] => 1989-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3424 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/961/04961170.pdf [firstpage_image] =>[orig_patent_app_number] => 452421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2759923 [patent_doc_number] => 05022008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'PROM speed measuring method' [patent_app_type] => 1 [patent_app_number] => 7/450711 [patent_app_country] => US [patent_app_date] => 1989-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3003 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/022/05022008.pdf [firstpage_image] =>[orig_patent_app_number] => 450711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2703210 [patent_doc_number] => 05020026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Method and apparatus for reading and programming electrically programmable memory cells' [patent_app_type] => 1 [patent_app_number] => 7/450702 [patent_app_country] => US [patent_app_date] => 1989-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4848 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/020/05020026.pdf [firstpage_image] =>[orig_patent_app_number] => 450702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2758687 [patent_doc_number] => 05031153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'MOS semiconductor memory device having sense control circuitry simplified' [patent_app_type] => 1 [patent_app_number] => 7/449562 [patent_app_country] => US [patent_app_date] => 1989-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/031/05031153.pdf [firstpage_image] =>[orig_patent_app_number] => 449562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2682892 [patent_doc_number] => 04984214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-08 [patent_title] => 'Multiplexed serial register architecture for VRAM' [patent_app_type] => 1 [patent_app_number] => 7/446032 [patent_app_country] => US [patent_app_date] => 1989-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4065 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/984/04984214.pdf [firstpage_image] =>[orig_patent_app_number] => 446032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2757126 [patent_doc_number] => 05016221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'First-in, first-out (FIFO) memory with variable commit point' [patent_app_type] => 1 [patent_app_number] => 7/444741 [patent_app_country] => US [patent_app_date] => 1989-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/016/05016221.pdf [firstpage_image] =>[orig_patent_app_number] => 444741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2753510 [patent_doc_number] => 05029137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Semiconductor memory device with tandem sense amplifier units' [patent_app_type] => 1 [patent_app_number] => 7/441662 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3555 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/029/05029137.pdf [firstpage_image] =>[orig_patent_app_number] => 441662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2680119 [patent_doc_number] => 05034925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Semiconductor memory device with redundancy responsive to advanced analysis' [patent_app_type] => 1 [patent_app_number] => 7/441661 [patent_app_country] => US [patent_app_date] => 1989-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2584 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034925.pdf [firstpage_image] =>[orig_patent_app_number] => 441661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2682947 [patent_doc_number] => 04984217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-08 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 7/440878 [patent_app_country] => US [patent_app_date] => 1989-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12696 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/984/04984217.pdf [firstpage_image] =>[orig_patent_app_number] => 440878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2678533 [patent_doc_number] => 05073873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/439870 [patent_app_country] => US [patent_app_date] => 1989-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 4383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073873.pdf [firstpage_image] =>[orig_patent_app_number] => 439870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2820213 [patent_doc_number] => 05086414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Semiconductor device having latch means' [patent_app_type] => 1 [patent_app_number] => 7/436770 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 52 [patent_no_of_words] => 13512 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086414.pdf [firstpage_image] =>[orig_patent_app_number] => 436770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2743808 [patent_doc_number] => 05051949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Content addressable memory device' [patent_app_type] => 1 [patent_app_number] => 7/437472 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3565 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051949.pdf [firstpage_image] =>[orig_patent_app_number] => 437472 [rel_patent_id] =>[rel_patent_doc_number] =>)