Lee D Wilson
Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )
Most Active Art Unit | 3723 |
Art Unit(s) | 3203, 3723, 3727 |
Total Applications | 4059 |
Issued Applications | 3286 |
Pending Applications | 170 |
Abandoned Applications | 602 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2612748
[patent_doc_number] => 04912674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-27
[patent_title] => 'Read-only memory'
[patent_app_type] => 1
[patent_app_number] => 7/310353
[patent_app_country] => US
[patent_app_date] => 1989-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 10012
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/912/04912674.pdf
[firstpage_image] =>[orig_patent_app_number] => 310353
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/310353 | Read-only memory | Feb 13, 1989 | Issued |
Array
(
[id] => 2790751
[patent_doc_number] => 05088066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-11
[patent_title] => 'Redundancy decoding circuit using n-channel transistors'
[patent_app_type] => 1
[patent_app_number] => 7/309320
[patent_app_country] => US
[patent_app_date] => 1989-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3247
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/088/05088066.pdf
[firstpage_image] =>[orig_patent_app_number] => 309320
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/309320 | Redundancy decoding circuit using n-channel transistors | Feb 9, 1989 | Issued |
Array
(
[id] => 2682929
[patent_doc_number] => 04984216
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Operation mode setting circuit for dram'
[patent_app_type] => 1
[patent_app_number] => 7/307701
[patent_app_country] => US
[patent_app_date] => 1989-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 5617
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984216.pdf
[firstpage_image] =>[orig_patent_app_number] => 307701
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/307701 | Operation mode setting circuit for dram | Feb 7, 1989 | Issued |
Array
(
[id] => 2823708
[patent_doc_number] => 05079746
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Semiconductor memory circuit'
[patent_app_type] => 1
[patent_app_number] => 7/306961
[patent_app_country] => US
[patent_app_date] => 1989-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 4611
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/079/05079746.pdf
[firstpage_image] =>[orig_patent_app_number] => 306961
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306961 | Semiconductor memory circuit | Feb 6, 1989 | Issued |
Array
(
[id] => 2755136
[patent_doc_number] => 05003512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-26
[patent_title] => 'Integrated memory circuit having a high-voltage switch'
[patent_app_type] => 1
[patent_app_number] => 7/306191
[patent_app_country] => US
[patent_app_date] => 1989-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 1789
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/003/05003512.pdf
[firstpage_image] =>[orig_patent_app_number] => 306191
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/306191 | Integrated memory circuit having a high-voltage switch | Feb 1, 1989 | Issued |
07/305192 | MAGNETIC BUBBLE RECORDING DEVICE | Feb 1, 1989 | Abandoned |
Array
(
[id] => 2742400
[patent_doc_number] => 05033026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-16
[patent_title] => 'Pseudo-static random access memory'
[patent_app_type] => 1
[patent_app_number] => 7/302891
[patent_app_country] => US
[patent_app_date] => 1989-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3814
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/033/05033026.pdf
[firstpage_image] =>[orig_patent_app_number] => 302891
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/302891 | Pseudo-static random access memory | Jan 29, 1989 | Issued |
Array
(
[id] => 2682711
[patent_doc_number] => 04984204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'High speed sensor system using a level shift circuit'
[patent_app_type] => 1
[patent_app_number] => 7/303472
[patent_app_country] => US
[patent_app_date] => 1989-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 30
[patent_no_of_words] => 22120
[patent_no_of_claims] => 89
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/984/04984204.pdf
[firstpage_image] =>[orig_patent_app_number] => 303472
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/303472 | High speed sensor system using a level shift circuit | Jan 29, 1989 | Issued |
Array
(
[id] => 2668035
[patent_doc_number] => 04979146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-18
[patent_title] => 'Electrically erasable non-volatile semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/302712
[patent_app_country] => US
[patent_app_date] => 1989-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 4703
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/979/04979146.pdf
[firstpage_image] =>[orig_patent_app_number] => 302712
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/302712 | Electrically erasable non-volatile semiconductor device | Jan 26, 1989 | Issued |
Array
(
[id] => 2753456
[patent_doc_number] => 05029134
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Memory circuit with improved serial access circuit arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/303492
[patent_app_country] => US
[patent_app_date] => 1989-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3506
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029134.pdf
[firstpage_image] =>[orig_patent_app_number] => 303492
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/303492 | Memory circuit with improved serial access circuit arrangement | Jan 26, 1989 | Issued |
Array
(
[id] => 2676856
[patent_doc_number] => 04935899
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-19
[patent_title] => 'Semiconductor memory device with redundant memory cells'
[patent_app_type] => 1
[patent_app_number] => 7/299092
[patent_app_country] => US
[patent_app_date] => 1989-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4869
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 379
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/935/04935899.pdf
[firstpage_image] =>[orig_patent_app_number] => 299092
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/299092 | Semiconductor memory device with redundant memory cells | Jan 18, 1989 | Issued |
Array
(
[id] => 2602735
[patent_doc_number] => 04918664
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-17
[patent_title] => 'Apparatus and method for preserving data integrity in multiple-port RAMS'
[patent_app_type] => 1
[patent_app_number] => 7/298472
[patent_app_country] => US
[patent_app_date] => 1989-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2786
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/918/04918664.pdf
[firstpage_image] =>[orig_patent_app_number] => 298472
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/298472 | Apparatus and method for preserving data integrity in multiple-port RAMS | Jan 17, 1989 | Issued |
Array
(
[id] => 2604000
[patent_doc_number] => 04933898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Secure integrated circuit chip with conductive shield'
[patent_app_type] => 1
[patent_app_number] => 7/297472
[patent_app_country] => US
[patent_app_date] => 1989-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6253
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/933/04933898.pdf
[firstpage_image] =>[orig_patent_app_number] => 297472
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/297472 | Secure integrated circuit chip with conductive shield | Jan 11, 1989 | Issued |
Array
(
[id] => 2626762
[patent_doc_number] => 04969126
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-06
[patent_title] => 'Semiconductor memory device having serial addressing and operating method thereof'
[patent_app_type] => 1
[patent_app_number] => 7/296021
[patent_app_country] => US
[patent_app_date] => 1989-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 6983
[patent_no_of_claims] => 27
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/969/04969126.pdf
[firstpage_image] =>[orig_patent_app_number] => 296021
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/296021 | Semiconductor memory device having serial addressing and operating method thereof | Jan 11, 1989 | Issued |
Array
(
[id] => 2857706
[patent_doc_number] => 05107458
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Bubble memory peripheral system tolerant to transient ionizing radiation'
[patent_app_type] => 1
[patent_app_number] => 7/294163
[patent_app_country] => US
[patent_app_date] => 1989-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 9967
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/107/05107458.pdf
[firstpage_image] =>[orig_patent_app_number] => 294163
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/294163 | Bubble memory peripheral system tolerant to transient ionizing radiation | Jan 5, 1989 | Issued |
Array
(
[id] => 2598703
[patent_doc_number] => 04959814
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Sensing detection circuit in dynamic random access memory'
[patent_app_type] => 1
[patent_app_number] => 7/290991
[patent_app_country] => US
[patent_app_date] => 1988-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959814.pdf
[firstpage_image] =>[orig_patent_app_number] => 290991
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/290991 | Sensing detection circuit in dynamic random access memory | Dec 27, 1988 | Issued |
Array
(
[id] => 2598666
[patent_doc_number] => 04959812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Electrically erasable programmable read-only memory with NAND cell structure'
[patent_app_type] => 1
[patent_app_number] => 7/289702
[patent_app_country] => US
[patent_app_date] => 1988-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959812.pdf
[firstpage_image] =>[orig_patent_app_number] => 289702
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/289702 | Electrically erasable programmable read-only memory with NAND cell structure | Dec 26, 1988 | Issued |
Array
(
[id] => 2598745
[patent_doc_number] => 04959816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-25
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/290721
[patent_app_country] => US
[patent_app_date] => 1988-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/959/04959816.pdf
[firstpage_image] =>[orig_patent_app_number] => 290721
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/290721 | Semiconductor integrated circuit | Dec 26, 1988 | Issued |
Array
(
[id] => 2655246
[patent_doc_number] => 04896296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-01-23
[patent_title] => 'Programmable logic device configurable input/output cell'
[patent_app_type] => 1
[patent_app_number] => 7/288945
[patent_app_country] => US
[patent_app_date] => 1988-12-23
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/896/04896296.pdf
[firstpage_image] =>[orig_patent_app_number] => 288945
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/288945 | Programmable logic device configurable input/output cell | Dec 22, 1988 | Issued |
Array
(
[id] => 2604206
[patent_doc_number] => 04933909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Dual read/write register file memory'
[patent_app_type] => 1
[patent_app_number] => 7/286552
[patent_app_country] => US
[patent_app_date] => 1988-12-19
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/933/04933909.pdf
[firstpage_image] =>[orig_patent_app_number] => 286552
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286552 | Dual read/write register file memory | Dec 18, 1988 | Issued |