Search

Lee D Wilson

Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3203, 3723, 3727
Total Applications
4059
Issued Applications
3286
Pending Applications
170
Abandoned Applications
602

Applications

Application numberTitle of the applicationFiling DateStatus
08/589139 CIRCUIT AND METHOD FOR TRACKING THE START OF A WRITE TO A MEMORY CELL Jan 18, 1996 Abandoned
Array ( [id] => 3699004 [patent_doc_number] => 05604694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Charge pump addressing' [patent_app_type] => 1 [patent_app_number] => 8/586138 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6017 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604694.pdf [firstpage_image] =>[orig_patent_app_number] => 586138 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/586138
Charge pump addressing Jan 15, 1996 Issued
Array ( [id] => 3674159 [patent_doc_number] => 05668753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Ferroelectric memory and method for controlling operation of the same' [patent_app_type] => 1 [patent_app_number] => 8/582734 [patent_app_country] => US [patent_app_date] => 1996-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 7602 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668753.pdf [firstpage_image] =>[orig_patent_app_number] => 582734 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/582734
Ferroelectric memory and method for controlling operation of the same Jan 3, 1996 Issued
Array ( [id] => 3853831 [patent_doc_number] => 05745416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/581740 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8227 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745416.pdf [firstpage_image] =>[orig_patent_app_number] => 581740 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581740
Non-volatile semiconductor memory device Dec 28, 1995 Issued
Array ( [id] => 3892613 [patent_doc_number] => 05748551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Memory device with multiple internal banks and staggered command execution' [patent_app_type] => 1 [patent_app_number] => 8/581034 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 8930 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748551.pdf [firstpage_image] =>[orig_patent_app_number] => 581034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581034
Memory device with multiple internal banks and staggered command execution Dec 28, 1995 Issued
Array ( [id] => 3671616 [patent_doc_number] => 05657280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Defective cell repairing circuit and method of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/580737 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5827 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657280.pdf [firstpage_image] =>[orig_patent_app_number] => 580737 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580737
Defective cell repairing circuit and method of semiconductor memory device Dec 28, 1995 Issued
Array ( [id] => 3712867 [patent_doc_number] => 05675536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/576331 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2357 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675536.pdf [firstpage_image] =>[orig_patent_app_number] => 576331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576331
Flash memory device Dec 20, 1995 Issued
Array ( [id] => 3703401 [patent_doc_number] => 05650974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Semiconductor memory device and power supply control IC for use with semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/575542 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9651 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650974.pdf [firstpage_image] =>[orig_patent_app_number] => 575542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575542
Semiconductor memory device and power supply control IC for use with semiconductor memory device Dec 19, 1995 Issued
Array ( [id] => 3706694 [patent_doc_number] => 05677869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Programming flash memory using strict ordering of states' [patent_app_type] => 1 [patent_app_number] => 8/572730 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7785 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677869.pdf [firstpage_image] =>[orig_patent_app_number] => 572730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572730
Programming flash memory using strict ordering of states Dec 13, 1995 Issued
Array ( [id] => 3633276 [patent_doc_number] => 05602785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'P-channel sense amplifier pull-up circuit with a timed pulse for use in DRAM memories having non-bootstrapped word lines' [patent_app_type] => 1 [patent_app_number] => 8/571532 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2852 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602785.pdf [firstpage_image] =>[orig_patent_app_number] => 571532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/571532
P-channel sense amplifier pull-up circuit with a timed pulse for use in DRAM memories having non-bootstrapped word lines Dec 12, 1995 Issued
Array ( [id] => 3843845 [patent_doc_number] => 05740113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/571135 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5155 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740113.pdf [firstpage_image] =>[orig_patent_app_number] => 571135 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/571135
Semiconductor memory device Dec 11, 1995 Issued
Array ( [id] => 3697843 [patent_doc_number] => 05663911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Semiconductor device having a booster circuit' [patent_app_type] => 1 [patent_app_number] => 8/568533 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5314 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663911.pdf [firstpage_image] =>[orig_patent_app_number] => 568533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568533
Semiconductor device having a booster circuit Dec 6, 1995 Issued
Array ( [id] => 3697962 [patent_doc_number] => 05691939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Triple poly PMOS flash memory cell' [patent_app_type] => 1 [patent_app_number] => 8/568835 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2981 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691939.pdf [firstpage_image] =>[orig_patent_app_number] => 568835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568835
Triple poly PMOS flash memory cell Dec 6, 1995 Issued
Array ( [id] => 3644015 [patent_doc_number] => 05631868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method and apparatus for testing redundant word and bit lines in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/563831 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3536 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631868.pdf [firstpage_image] =>[orig_patent_app_number] => 563831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563831
Method and apparatus for testing redundant word and bit lines in a memory array Nov 27, 1995 Issued
Array ( [id] => 3739216 [patent_doc_number] => 05703821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'High performance single port RAM generator architecture' [patent_app_type] => 1 [patent_app_number] => 8/562736 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2904 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703821.pdf [firstpage_image] =>[orig_patent_app_number] => 562736 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562736
High performance single port RAM generator architecture Nov 26, 1995 Issued
Array ( [id] => 3643970 [patent_doc_number] => 05631865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Data outputting circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/562745 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631865.pdf [firstpage_image] =>[orig_patent_app_number] => 562745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/562745
Data outputting circuit for semiconductor memory device Nov 26, 1995 Issued
Array ( [id] => 3657619 [patent_doc_number] => 05640342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Structure for cross coupled thin film transistors and static random access memory cell' [patent_app_type] => 1 [patent_app_number] => 8/561131 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640342.pdf [firstpage_image] =>[orig_patent_app_number] => 561131 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/561131
Structure for cross coupled thin film transistors and static random access memory cell Nov 19, 1995 Issued
Array ( [id] => 3740906 [patent_doc_number] => 05666309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold' [patent_app_type] => 1 [patent_app_number] => 8/560038 [patent_app_country] => US [patent_app_date] => 1995-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2290 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666309.pdf [firstpage_image] =>[orig_patent_app_number] => 560038 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/560038
Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold Nov 16, 1995 Issued
Array ( [id] => 3703764 [patent_doc_number] => 05661686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/555232 [patent_app_country] => US [patent_app_date] => 1995-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 10850 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661686.pdf [firstpage_image] =>[orig_patent_app_number] => 555232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/555232
Nonvolatile semiconductor memory Nov 7, 1995 Issued
Array ( [id] => 3867611 [patent_doc_number] => 05706229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/553035 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11547 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706229.pdf [firstpage_image] =>[orig_patent_app_number] => 553035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/553035
Semiconductor memory device Nov 2, 1995 Issued
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