Lee D Wilson
Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )
Most Active Art Unit | 3723 |
Art Unit(s) | 3203, 3723, 3727 |
Total Applications | 4059 |
Issued Applications | 3286 |
Pending Applications | 170 |
Abandoned Applications | 602 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2558308
[patent_doc_number] => 04811297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-03-07
[patent_title] => 'Boundary-free semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/132442
[patent_app_country] => US
[patent_app_date] => 1987-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 48
[patent_no_of_words] => 10259
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/811/04811297.pdf
[firstpage_image] =>[orig_patent_app_number] => 132442
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/132442 | Boundary-free semiconductor memory device | Dec 13, 1987 | Issued |
Array
(
[id] => 2572735
[patent_doc_number] => 04849940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Optical neural net memory'
[patent_app_type] => 1
[patent_app_number] => 7/131012
[patent_app_country] => US
[patent_app_date] => 1987-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4904
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/849/04849940.pdf
[firstpage_image] =>[orig_patent_app_number] => 131012
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/131012 | Optical neural net memory | Dec 9, 1987 | Issued |
Array
(
[id] => 2486726
[patent_doc_number] => 04876670
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-24
[patent_title] => 'Variable delay circuit for delaying input data'
[patent_app_type] => 1
[patent_app_number] => 7/130741
[patent_app_country] => US
[patent_app_date] => 1987-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 4884
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/876/04876670.pdf
[firstpage_image] =>[orig_patent_app_number] => 130741
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/130741 | Variable delay circuit for delaying input data | Dec 8, 1987 | Issued |
Array
(
[id] => 2606806
[patent_doc_number] => 04965768
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-23
[patent_title] => 'Semiconductor device having programmable read only memory cells for specific mode'
[patent_app_type] => 1
[patent_app_number] => 7/130691
[patent_app_country] => US
[patent_app_date] => 1987-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3514
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/965/04965768.pdf
[firstpage_image] =>[orig_patent_app_number] => 130691
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/130691 | Semiconductor device having programmable read only memory cells for specific mode | Dec 7, 1987 | Issued |
Array
(
[id] => 2539473
[patent_doc_number] => 04839859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-13
[patent_title] => 'High density associative memory'
[patent_app_type] => 1
[patent_app_number] => 7/128872
[patent_app_country] => US
[patent_app_date] => 1987-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3946
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/839/04839859.pdf
[firstpage_image] =>[orig_patent_app_number] => 128872
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/128872 | High density associative memory | Dec 3, 1987 | Issued |
Array
(
[id] => 2552472
[patent_doc_number] => 04827453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-02
[patent_title] => 'Semiconductor memory control circuit'
[patent_app_type] => 1
[patent_app_number] => 7/127261
[patent_app_country] => US
[patent_app_date] => 1987-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3246
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/827/04827453.pdf
[firstpage_image] =>[orig_patent_app_number] => 127261
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/127261 | Semiconductor memory control circuit | Nov 30, 1987 | Issued |
Array
(
[id] => 2527786
[patent_doc_number] => 04870621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-09-26
[patent_title] => 'Dual port memory device with improved serial access scheme'
[patent_app_type] => 1
[patent_app_number] => 7/127022
[patent_app_country] => US
[patent_app_date] => 1987-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3382
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/870/04870621.pdf
[firstpage_image] =>[orig_patent_app_number] => 127022
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/127022 | Dual port memory device with improved serial access scheme | Nov 26, 1987 | Issued |
Array
(
[id] => 2500913
[patent_doc_number] => 04860257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-22
[patent_title] => 'Level shifter for an input/output bus in a CMOS dynamic ram'
[patent_app_type] => 1
[patent_app_number] => 7/125682
[patent_app_country] => US
[patent_app_date] => 1987-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2133
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/860/04860257.pdf
[firstpage_image] =>[orig_patent_app_number] => 125682
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/125682 | Level shifter for an input/output bus in a CMOS dynamic ram | Nov 24, 1987 | Issued |
07/122692 | NON-DESTRUCTIVE READ FERROELECTRIC BASED MEMORY CIRCUIT | Nov 18, 1987 | Abandoned |
Array
(
[id] => 2498165
[patent_doc_number] => 04802132
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-01-31
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/122332
[patent_app_country] => US
[patent_app_date] => 1987-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 30
[patent_no_of_words] => 9497
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/802/04802132.pdf
[firstpage_image] =>[orig_patent_app_number] => 122332
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/122332 | Semiconductor memory device | Nov 17, 1987 | Issued |
Array
(
[id] => 2574468
[patent_doc_number] => 04858189
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-15
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/121914
[patent_app_country] => US
[patent_app_date] => 1987-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 11410
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/858/04858189.pdf
[firstpage_image] =>[orig_patent_app_number] => 121914
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/121914 | Semiconductor integrated circuit | Nov 16, 1987 | Issued |
Array
(
[id] => 2570383
[patent_doc_number] => 04837744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-06
[patent_title] => 'Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 7/116692
[patent_app_country] => US
[patent_app_date] => 1987-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2333
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/837/04837744.pdf
[firstpage_image] =>[orig_patent_app_number] => 116692
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/116692 | Integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory | Nov 3, 1987 | Issued |
07/114311 | SEMICONDUCTOR MEMORY DEVICE | Oct 26, 1987 | Abandoned |
Array
(
[id] => 2520085
[patent_doc_number] => 04831585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-16
[patent_title] => 'Four transistor cross-coupled bitline content addressable memory'
[patent_app_type] => 1
[patent_app_number] => 7/115585
[patent_app_country] => US
[patent_app_date] => 1987-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4739
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/831/04831585.pdf
[firstpage_image] =>[orig_patent_app_number] => 115585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/115585 | Four transistor cross-coupled bitline content addressable memory | Oct 25, 1987 | Issued |
07/087071 | CONTROL CIRCUITS | Oct 22, 1987 | Abandoned |
Array
(
[id] => 2528386
[patent_doc_number] => 04855951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-08
[patent_title] => 'Method for erasing recording in a PHB memory'
[patent_app_type] => 1
[patent_app_number] => 7/111611
[patent_app_country] => US
[patent_app_date] => 1987-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 3011
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/855/04855951.pdf
[firstpage_image] =>[orig_patent_app_number] => 111611
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/111611 | Method for erasing recording in a PHB memory | Oct 22, 1987 | Issued |
Array
(
[id] => 2528479
[patent_doc_number] => 04855956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-08
[patent_title] => 'Semiconductor memory device with improved cell arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/103312
[patent_app_country] => US
[patent_app_date] => 1987-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2873
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/855/04855956.pdf
[firstpage_image] =>[orig_patent_app_number] => 103312
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/103312 | Semiconductor memory device with improved cell arrangement | Sep 30, 1987 | Issued |
Array
(
[id] => 2539549
[patent_doc_number] => 04839863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-13
[patent_title] => 'Memory cell circuit'
[patent_app_type] => 1
[patent_app_number] => 7/101441
[patent_app_country] => US
[patent_app_date] => 1987-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3001
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/839/04839863.pdf
[firstpage_image] =>[orig_patent_app_number] => 101441
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/101441 | Memory cell circuit | Sep 27, 1987 | Issued |
Array
(
[id] => 2400768
[patent_doc_number] => 04782467
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-11-01
[patent_title] => 'Radiation hard gated feedback memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/102304
[patent_app_country] => US
[patent_app_date] => 1987-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4844
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/782/04782467.pdf
[firstpage_image] =>[orig_patent_app_number] => 102304
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/102304 | Radiation hard gated feedback memory cell | Sep 24, 1987 | Issued |
Array
(
[id] => 2572714
[patent_doc_number] => 04849939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Semiconductor memorizing device'
[patent_app_type] => 1
[patent_app_number] => 7/100752
[patent_app_country] => US
[patent_app_date] => 1987-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 10389
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/849/04849939.pdf
[firstpage_image] =>[orig_patent_app_number] => 100752
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/100752 | Semiconductor memorizing device | Sep 23, 1987 | Issued |