Lee D Wilson
Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )
Most Active Art Unit | 3723 |
Art Unit(s) | 3203, 3723, 3727 |
Total Applications | 4059 |
Issued Applications | 3286 |
Pending Applications | 170 |
Abandoned Applications | 602 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2453080
[patent_doc_number] => 04740924
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-04-26
[patent_title] => 'Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals'
[patent_app_type] => 1
[patent_app_number] => 6/828513
[patent_app_country] => US
[patent_app_date] => 1986-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2732
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 480
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/740/04740924.pdf
[firstpage_image] =>[orig_patent_app_number] => 828513
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/828513 | Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals | Feb 11, 1986 | Issued |
Array
(
[id] => 2428956
[patent_doc_number] => 04734888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-03-29
[patent_title] => 'Circuit arrangement comprising a matrix shaped memory arrangement for variably adjustable time delay of digital signals'
[patent_app_type] => 1
[patent_app_number] => 6/828512
[patent_app_country] => US
[patent_app_date] => 1986-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2435
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[pdf_file] => patents/04/734/04734888.pdf
[firstpage_image] =>[orig_patent_app_number] => 828512
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/828512 | Circuit arrangement comprising a matrix shaped memory arrangement for variably adjustable time delay of digital signals | Feb 11, 1986 | Issued |
Array
(
[id] => 2427960
[patent_doc_number] => 04727514
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-02-23
[patent_title] => 'Programmable memory with memory cells programmed by addressing'
[patent_app_type] => 1
[patent_app_number] => 6/828469
[patent_app_country] => US
[patent_app_date] => 1986-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4416
[patent_no_of_claims] => 16
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/727/04727514.pdf
[firstpage_image] =>[orig_patent_app_number] => 828469
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/828469 | Programmable memory with memory cells programmed by addressing | Feb 10, 1986 | Issued |
Array
(
[id] => 2453143
[patent_doc_number] => 04745579
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-05-17
[patent_title] => 'Electrically erasable programmable logic array (EEPLA)'
[patent_app_type] => 1
[patent_app_number] => 6/837388
[patent_app_country] => US
[patent_app_date] => 1986-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10529
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/745/04745579.pdf
[firstpage_image] =>[orig_patent_app_number] => 837388
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/837388 | Electrically erasable programmable logic array (EEPLA) | Feb 6, 1986 | Issued |
Array
(
[id] => 2456349
[patent_doc_number] => 04723229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-02-02
[patent_title] => 'Integrated memory circuit having an improved logic row selection gate'
[patent_app_type] => 1
[patent_app_number] => 6/825842
[patent_app_country] => US
[patent_app_date] => 1986-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1632
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/723/04723229.pdf
[firstpage_image] =>[orig_patent_app_number] => 825842
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/825842 | Integrated memory circuit having an improved logic row selection gate | Feb 3, 1986 | Issued |
06/825939 | SEMICONDUCTOR DEVICE | Feb 3, 1986 | Abandoned |
Array
(
[id] => 2460013
[patent_doc_number] => 04733373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-03-22
[patent_title] => 'Dynamic memory with improved arrangement for precharging bit lines'
[patent_app_type] => 1
[patent_app_number] => 6/824030
[patent_app_country] => US
[patent_app_date] => 1986-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3625
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/733/04733373.pdf
[firstpage_image] =>[orig_patent_app_number] => 824030
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/824030 | Dynamic memory with improved arrangement for precharging bit lines | Jan 29, 1986 | Issued |
Array
(
[id] => 2341388
[patent_doc_number] => 04712197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-08
[patent_title] => 'High speed equalization in a memory'
[patent_app_type] => 1
[patent_app_number] => 6/823446
[patent_app_country] => US
[patent_app_date] => 1986-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7438
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/712/04712197.pdf
[firstpage_image] =>[orig_patent_app_number] => 823446
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/823446 | High speed equalization in a memory | Jan 27, 1986 | Issued |
Array
(
[id] => 2458508
[patent_doc_number] => 04758995
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-07-19
[patent_title] => 'Semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 6/820326
[patent_app_country] => US
[patent_app_date] => 1986-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 12701
[patent_no_of_claims] => 28
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[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/758/04758995.pdf
[firstpage_image] =>[orig_patent_app_number] => 820326
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/820326 | Semiconductor memory | Jan 20, 1986 | Issued |
Array
(
[id] => 2458489
[patent_doc_number] => 04758994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-07-19
[patent_title] => 'On chip voltage regulator for common collector matrix programmable memory array'
[patent_app_type] => 1
[patent_app_number] => 6/820286
[patent_app_country] => US
[patent_app_date] => 1986-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3312
[patent_no_of_claims] => 12
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/758/04758994.pdf
[firstpage_image] =>[orig_patent_app_number] => 820286
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/820286 | On chip voltage regulator for common collector matrix programmable memory array | Jan 16, 1986 | Issued |
Array
(
[id] => 2393093
[patent_doc_number] => 04707810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-11-17
[patent_title] => 'Integrated circuit memory'
[patent_app_type] => 1
[patent_app_number] => 6/818031
[patent_app_country] => US
[patent_app_date] => 1986-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4897
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/707/04707810.pdf
[firstpage_image] =>[orig_patent_app_number] => 818031
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/818031 | Integrated circuit memory | Jan 12, 1986 | Issued |
Array
(
[id] => 2464535
[patent_doc_number] => 04718041
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-01-05
[patent_title] => 'EEPROM memory having extended life'
[patent_app_type] => 1
[patent_app_number] => 6/817382
[patent_app_country] => US
[patent_app_date] => 1986-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 7461
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/718/04718041.pdf
[firstpage_image] =>[orig_patent_app_number] => 817382
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/817382 | EEPROM memory having extended life | Jan 8, 1986 | Issued |
Array
(
[id] => 2456226
[patent_doc_number] => 04723224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-02-02
[patent_title] => 'Content addressable memory having field masking'
[patent_app_type] => 1
[patent_app_number] => 6/815610
[patent_app_country] => US
[patent_app_date] => 1986-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/723/04723224.pdf
[firstpage_image] =>[orig_patent_app_number] => 815610
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/815610 | Content addressable memory having field masking | Jan 1, 1986 | Issued |
Array
(
[id] => 2345297
[patent_doc_number] => 04669066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-05-26
[patent_title] => 'Memory data holding circuit'
[patent_app_type] => 1
[patent_app_number] => 6/816122
[patent_app_country] => US
[patent_app_date] => 1985-12-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/669/04669066.pdf
[firstpage_image] =>[orig_patent_app_number] => 816122
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/816122 | Memory data holding circuit | Dec 30, 1985 | Issued |
Array
(
[id] => 2298461
[patent_doc_number] => 04710900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-12-01
[patent_title] => 'Non-volatile semiconductor memory device having an improved write circuit'
[patent_app_type] => 1
[patent_app_number] => 6/814472
[patent_app_country] => US
[patent_app_date] => 1985-12-30
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/710/04710900.pdf
[firstpage_image] =>[orig_patent_app_number] => 814472
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/814472 | Non-volatile semiconductor memory device having an improved write circuit | Dec 29, 1985 | Issued |
Array
(
[id] => 2455939
[patent_doc_number] => 04755970
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-07-05
[patent_title] => 'Method and apparatus for functional testing of a memory which is reprogrammable electrically word by word'
[patent_app_type] => 1
[patent_app_number] => 6/814620
[patent_app_country] => US
[patent_app_date] => 1985-12-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/755/04755970.pdf
[firstpage_image] =>[orig_patent_app_number] => 814620
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/814620 | Method and apparatus for functional testing of a memory which is reprogrammable electrically word by word | Dec 29, 1985 | Issued |
Array
(
[id] => 2451519
[patent_doc_number] => 04779235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-10-18
[patent_title] => 'Parallel operation optical processor unit'
[patent_app_type] => 1
[patent_app_number] => 6/814471
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/779/04779235.pdf
[firstpage_image] =>[orig_patent_app_number] => 814471
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/814471 | Parallel operation optical processor unit | Dec 29, 1985 | Issued |
Array
(
[id] => 2430995
[patent_doc_number] => 04780851
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-10-25
[patent_title] => 'Semiconductor memory device having improved redundant structure'
[patent_app_type] => 1
[patent_app_number] => 6/813216
[patent_app_country] => US
[patent_app_date] => 1985-12-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/780/04780851.pdf
[firstpage_image] =>[orig_patent_app_number] => 813216
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/813216 | Semiconductor memory device having improved redundant structure | Dec 23, 1985 | Issued |
Array
(
[id] => 2422269
[patent_doc_number] => 04742489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-05-03
[patent_title] => 'Integrated semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 6/811886
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[pdf_file] => patents/04/742/04742489.pdf
[firstpage_image] =>[orig_patent_app_number] => 811886
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/811886 | Integrated semiconductor memory | Dec 19, 1985 | Issued |
Array
(
[id] => 2309981
[patent_doc_number] => 04691300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-09-01
[patent_title] => 'Redundant column substitution architecture with improved column access time'
[patent_app_type] => 1
[patent_app_number] => 6/811856
[patent_app_country] => US
[patent_app_date] => 1985-12-20
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[pdf_file] => patents/04/691/04691300.pdf
[firstpage_image] =>[orig_patent_app_number] => 811856
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/811856 | Redundant column substitution architecture with improved column access time | Dec 19, 1985 | Issued |