
Lee D Wilson
Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )
Most Active Art Unit | 3723 |
Art Unit(s) | 3203, 3723, 3727 |
Total Applications | 4059 |
Issued Applications | 3286 |
Pending Applications | 170 |
Abandoned Applications | 602 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2317278
[patent_doc_number] => 04638459
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-20
[patent_title] => 'Virtual ground read only memory'
[patent_app_type] => 1
[patent_app_number] => 6/696591
[patent_app_country] => US
[patent_app_date] => 1985-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2564
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/638/04638459.pdf
[firstpage_image] =>[orig_patent_app_number] => 696591
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/696591 | Virtual ground read only memory | Jan 30, 1985 | Issued |
Array
(
[id] => 2350053
[patent_doc_number] => 04641284
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-03
[patent_title] => 'Signal transmission circuit for a storage device'
[patent_app_type] => 1
[patent_app_number] => 6/696142
[patent_app_country] => US
[patent_app_date] => 1985-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5160
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/641/04641284.pdf
[firstpage_image] =>[orig_patent_app_number] => 696142
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/696142 | Signal transmission circuit for a storage device | Jan 28, 1985 | Issued |
Array
(
[id] => 2317903
[patent_doc_number] => 04646265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-24
[patent_title] => 'Serial ROM devices'
[patent_app_type] => 1
[patent_app_number] => 6/695776
[patent_app_country] => US
[patent_app_date] => 1985-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 8569
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/646/04646265.pdf
[firstpage_image] =>[orig_patent_app_number] => 695776
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/695776 | Serial ROM devices | Jan 27, 1985 | Issued |
Array
(
[id] => 2364920
[patent_doc_number] => 04648077
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-03
[patent_title] => 'Video serial accessed memory with midline load'
[patent_app_type] => 1
[patent_app_number] => 6/693422
[patent_app_country] => US
[patent_app_date] => 1985-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 15015
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/648/04648077.pdf
[firstpage_image] =>[orig_patent_app_number] => 693422
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/693422 | Video serial accessed memory with midline load | Jan 21, 1985 | Issued |
Array
(
[id] => 2364800
[patent_doc_number] => 04667313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-05-19
[patent_title] => 'Serially accessed semiconductor memory with tapped shift register'
[patent_app_type] => 1
[patent_app_number] => 6/693424
[patent_app_country] => US
[patent_app_date] => 1985-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 14988
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/667/04667313.pdf
[firstpage_image] =>[orig_patent_app_number] => 693424
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/693424 | Serially accessed semiconductor memory with tapped shift register | Jan 21, 1985 | Issued |
Array
(
[id] => 2331795
[patent_doc_number] => 04636986
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-13
[patent_title] => 'Separately addressable memory arrays in a multiple array semiconductor chip'
[patent_app_type] => 1
[patent_app_number] => 6/693421
[patent_app_country] => US
[patent_app_date] => 1985-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 14968
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/636/04636986.pdf
[firstpage_image] =>[orig_patent_app_number] => 693421
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/693421 | Separately addressable memory arrays in a multiple array semiconductor chip | Jan 21, 1985 | Issued |
Array
(
[id] => 2335376
[patent_doc_number] => 04672584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-06-09
[patent_title] => 'CMOS integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 6/691701
[patent_app_country] => US
[patent_app_date] => 1985-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3755
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/672/04672584.pdf
[firstpage_image] =>[orig_patent_app_number] => 691701
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/691701 | CMOS integrated circuit | Jan 14, 1985 | Issued |
Array
(
[id] => 2283560
[patent_doc_number] => 04607351
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-08-19
[patent_title] => 'Cartridge memory protection'
[patent_app_type] => 1
[patent_app_number] => 6/691022
[patent_app_country] => US
[patent_app_date] => 1985-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2630
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/607/04607351.pdf
[firstpage_image] =>[orig_patent_app_number] => 691022
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/691022 | Cartridge memory protection | Jan 13, 1985 | Issued |
Array
(
[id] => 2287194
[patent_doc_number] => 04627031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-12-02
[patent_title] => 'CMOS memory arrangement'
[patent_app_type] => 1
[patent_app_number] => 6/689256
[patent_app_country] => US
[patent_app_date] => 1985-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 3659
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/627/04627031.pdf
[firstpage_image] =>[orig_patent_app_number] => 689256
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/689256 | CMOS memory arrangement | Jan 6, 1985 | Issued |
Array
(
[id] => 2297920
[patent_doc_number] => 04639896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-27
[patent_title] => 'Redundant row decoding for programmable devices'
[patent_app_type] => 1
[patent_app_number] => 6/676846
[patent_app_country] => US
[patent_app_date] => 1984-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1639
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/639/04639896.pdf
[firstpage_image] =>[orig_patent_app_number] => 676846
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/676846 | Redundant row decoding for programmable devices | Nov 29, 1984 | Issued |
Array
(
[id] => 2309677
[patent_doc_number] => 04642799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-10
[patent_title] => 'System and process for optical processing of information'
[patent_app_type] => 1
[patent_app_number] => 6/676676
[patent_app_country] => US
[patent_app_date] => 1984-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4007
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/642/04642799.pdf
[firstpage_image] =>[orig_patent_app_number] => 676676
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/676676 | System and process for optical processing of information | Nov 29, 1984 | Issued |
Array
(
[id] => 2347680
[patent_doc_number] => 04661928
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-04-28
[patent_title] => 'Output buffer in which inductive noise is suppressed'
[patent_app_type] => 1
[patent_app_number] => 6/675586
[patent_app_country] => US
[patent_app_date] => 1984-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5927
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/661/04661928.pdf
[firstpage_image] =>[orig_patent_app_number] => 675586
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/675586 | Output buffer in which inductive noise is suppressed | Nov 27, 1984 | Issued |
Array
(
[id] => 2332928
[patent_doc_number] => 04698787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-10-06
[patent_title] => 'Single transistor electrically programmable memory device and method'
[patent_app_type] => 1
[patent_app_number] => 6/673946
[patent_app_country] => US
[patent_app_date] => 1984-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7131
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/698/04698787.pdf
[firstpage_image] =>[orig_patent_app_number] => 673946
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/673946 | Single transistor electrically programmable memory device and method | Nov 20, 1984 | Issued |
Array
(
[id] => 2360809
[patent_doc_number] => 04651308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-17
[patent_title] => 'LSI memory circuit'
[patent_app_type] => 1
[patent_app_number] => 6/673392
[patent_app_country] => US
[patent_app_date] => 1984-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 1674
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/651/04651308.pdf
[firstpage_image] =>[orig_patent_app_number] => 673392
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/673392 | LSI memory circuit | Nov 20, 1984 | Issued |
Array
(
[id] => 2364916
[patent_doc_number] => 04648075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-03-03
[patent_title] => 'Redundancy circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 6/669361
[patent_app_country] => US
[patent_app_date] => 1984-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3385
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/648/04648075.pdf
[firstpage_image] =>[orig_patent_app_number] => 669361
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/669361 | Redundancy circuit for a semiconductor memory device | Nov 7, 1984 | Issued |
Array
(
[id] => 2331692
[patent_doc_number] => 04636979
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-01-13
[patent_title] => 'Orientation of reference cells in a memory'
[patent_app_type] => 1
[patent_app_number] => 6/667943
[patent_app_country] => US
[patent_app_date] => 1984-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 6020
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/636/04636979.pdf
[firstpage_image] =>[orig_patent_app_number] => 667943
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/667943 | Orientation of reference cells in a memory | Nov 1, 1984 | Issued |
Array
(
[id] => 2420959
[patent_doc_number] => 04725985
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-02-16
[patent_title] => 'Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 6/667162
[patent_app_country] => US
[patent_app_date] => 1984-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3391
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/725/04725985.pdf
[firstpage_image] =>[orig_patent_app_number] => 667162
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/667162 | Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device | Oct 31, 1984 | Issued |
Array
(
[id] => 2286734
[patent_doc_number] => 04623990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-11-18
[patent_title] => 'Dual-port read/write RAM with single array'
[patent_app_type] => 1
[patent_app_number] => 6/667022
[patent_app_country] => US
[patent_app_date] => 1984-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 10131
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/623/04623990.pdf
[firstpage_image] =>[orig_patent_app_number] => 667022
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/667022 | Dual-port read/write RAM with single array | Oct 30, 1984 | Issued |
Array
(
[id] => 2247707
[patent_doc_number] => 04622653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1986-11-11
[patent_title] => 'Block associative memory'
[patent_app_type] => 1
[patent_app_number] => 6/666012
[patent_app_country] => US
[patent_app_date] => 1984-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 6005
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/622/04622653.pdf
[firstpage_image] =>[orig_patent_app_number] => 666012
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/666012 | Block associative memory | Oct 28, 1984 | Issued |
Array
(
[id] => 2309679
[patent_doc_number] => 04644504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1987-02-17
[patent_title] => 'Programmable CMOS circuit for user defined chip enable and output enable'
[patent_app_type] => 1
[patent_app_number] => 6/664822
[patent_app_country] => US
[patent_app_date] => 1984-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 4119
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/644/04644504.pdf
[firstpage_image] =>[orig_patent_app_number] => 664822
[rel_patent_id] =>[rel_patent_doc_number] =>) 06/664822 | Programmable CMOS circuit for user defined chip enable and output enable | Oct 24, 1984 | Issued |