Lee D Wilson

Array ( [id] => 2205071 [patent_doc_number] => 04542483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-09-17 [patent_title] => 'Dual stage sense amplifier for dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 6/557632 [patent_app_country] => US [patent_app_date] => 1983-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2772 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/542/04542483.pdf [firstpage_image] =>[orig_patent_app_number] => 557632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2225765 [patent_doc_number] => 04578776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'Dynamic semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 6/555891 [patent_app_country] => US [patent_app_date] => 1983-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5843 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578776.pdf [firstpage_image] =>[orig_patent_app_number] => 555891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2286716 [patent_doc_number] => 04602353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-22 [patent_title] => 'Integrated semiconductor circuit with a dynamic read-write memory' [patent_app_type] => 1 [patent_app_number] => 6/554432 [patent_app_country] => US [patent_app_date] => 1983-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7109 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/602/04602353.pdf [firstpage_image] =>[orig_patent_app_number] => 554432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2275666 [patent_doc_number] => 04584674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-22 [patent_title] => 'Semiconductor memory device with improved memory arrangement' [patent_app_type] => 1 [patent_app_number] => 6/552221 [patent_app_country] => US [patent_app_date] => 1983-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/584/04584674.pdf [firstpage_image] =>[orig_patent_app_number] => 552221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2241093 [patent_doc_number] => 04574367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-04 [patent_title] => 'Memory cell and array' [patent_app_type] => 1 [patent_app_number] => 6/551736 [patent_app_country] => US [patent_app_date] => 1983-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3530 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/574/04574367.pdf [firstpage_image] =>[orig_patent_app_number] => 551736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2269304 [patent_doc_number] => 04580246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-01 [patent_title] => 'Write protection circuit and method for a control register' [patent_app_type] => 1 [patent_app_number] => 6/548171 [patent_app_country] => US [patent_app_date] => 1983-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3546 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/580/04580246.pdf [firstpage_image] =>[orig_patent_app_number] => 548171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2272980 [patent_doc_number] => 04612629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-16 [patent_title] => 'Highly scalable dynamic RAM cell with self-signal amplification' [patent_app_type] => 1 [patent_app_number] => 6/537477 [patent_app_country] => US [patent_app_date] => 1983-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 18647 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/612/04612629.pdf [firstpage_image] =>[orig_patent_app_number] => 537477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2266180 [patent_doc_number] => 04598387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-01 [patent_title] => 'Capacitive memory signal doubler cell' [patent_app_type] => 1 [patent_app_number] => 6/537319 [patent_app_country] => US [patent_app_date] => 1983-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4267 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/598/04598387.pdf [firstpage_image] =>[orig_patent_app_number] => 537319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2225833 [patent_doc_number] => 04578780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'Dual port type semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 6/536321 [patent_app_country] => US [patent_app_date] => 1983-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2034 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578780.pdf [firstpage_image] =>[orig_patent_app_number] => 536321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2281728 [patent_doc_number] => 04581720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-08 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 6/535836 [patent_app_country] => US [patent_app_date] => 1983-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/581/04581720.pdf [firstpage_image] =>[orig_patent_app_number] => 535836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2266300 [patent_doc_number] => 04564925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-01-14 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 6/535056 [patent_app_country] => US [patent_app_date] => 1983-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9224 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/564/04564925.pdf [firstpage_image] =>[orig_patent_app_number] => 535056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2182701 [patent_doc_number] => 04562555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-12-31 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 6/535232 [patent_app_country] => US [patent_app_date] => 1983-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7174 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/562/04562555.pdf [firstpage_image] =>[orig_patent_app_number] => 535232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2286743 [patent_doc_number] => 04602355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-22 [patent_title] => 'Memory circuit with noise preventing means for word lines' [patent_app_type] => 1 [patent_app_number] => 6/531372 [patent_app_country] => US [patent_app_date] => 1983-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3904 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/602/04602355.pdf [firstpage_image] =>[orig_patent_app_number] => 531372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2227400 [patent_doc_number] => 04583201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-15 [patent_title] => 'Resistor personalized memory device using a resistive gate fet' [patent_app_type] => 1 [patent_app_number] => 6/530451 [patent_app_country] => US [patent_app_date] => 1983-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2503 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/583/04583201.pdf [firstpage_image] =>[orig_patent_app_number] => 530451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2205540 [patent_doc_number] => 04549283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-10-22 [patent_title] => 'Digital time delay circuit with high speed and large delay capacity' [patent_app_type] => 1 [patent_app_number] => 6/529302 [patent_app_country] => US [patent_app_date] => 1983-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1911 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/549/04549283.pdf [firstpage_image] =>[orig_patent_app_number] => 529302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2225278 [patent_doc_number] => 04631707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-23 [patent_title] => 'Memory circuit with power supply voltage detection means' [patent_app_type] => 1 [patent_app_number] => 6/528006 [patent_app_country] => US [patent_app_date] => 1983-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/631/04631707.pdf [firstpage_image] =>[orig_patent_app_number] => 528006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2290989 [patent_doc_number] => 04604727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-05 [patent_title] => 'Memory with configuration RAM' [patent_app_type] => 1 [patent_app_number] => 6/528303 [patent_app_country] => US [patent_app_date] => 1983-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 16 [patent_no_of_words] => 9425 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/604/04604727.pdf [firstpage_image] =>[orig_patent_app_number] => 528303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2225866 [patent_doc_number] => 04578782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'Asynchronous memory refresh arbitration circuit' [patent_app_type] => 1 [patent_app_number] => 6/526736 [patent_app_country] => US [patent_app_date] => 1983-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578782.pdf [firstpage_image] =>[orig_patent_app_number] => 526736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2257096 [patent_doc_number] => 04603405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-29 [patent_title] => 'Monolithically integrated semiconductor circuit' [patent_app_type] => 1 [patent_app_number] => 6/524881 [patent_app_country] => US [patent_app_date] => 1983-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/603/04603405.pdf [firstpage_image] =>[orig_patent_app_number] => 524881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2100979 [patent_doc_number] => 04475177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-02 [patent_title] => 'Non-volatile semiconductor memory circuits' [patent_app_type] => 1 [patent_app_number] => 6/520744 [patent_app_country] => US [patent_app_date] => 1983-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2233 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/475/04475177.pdf [firstpage_image] =>[orig_patent_app_number] => 520744 [rel_patent_id] =>[rel_patent_doc_number] =>)