Search

Lee D Wilson

Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3203, 3723, 3727
Total Applications
4059
Issued Applications
3286
Pending Applications
170
Abandoned Applications
602

Applications

Application numberTitle of the applicationFiling DateStatus
08/523861 RECORDING/REPRODUCING METHOD AND RECORDING/REPRODUCING APPARATUS Sep 5, 1995 Abandoned
Array ( [id] => 3630706 [patent_doc_number] => 05615169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and structure for controlling internal operations of a DRAM array' [patent_app_type] => 1 [patent_app_number] => 8/522032 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5038 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615169.pdf [firstpage_image] =>[orig_patent_app_number] => 522032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522032
Method and structure for controlling internal operations of a DRAM array Aug 30, 1995 Issued
Array ( [id] => 3706990 [patent_doc_number] => 05677889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Static type semiconductor device operable at a low voltage with small power consumption' [patent_app_type] => 1 [patent_app_number] => 8/517030 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677889.pdf [firstpage_image] =>[orig_patent_app_number] => 517030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/517030
Static type semiconductor device operable at a low voltage with small power consumption Aug 17, 1995 Issued
Array ( [id] => 3664479 [patent_doc_number] => 05623444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Electrically-erasable ROM with pulse-driven memory cell transistors' [patent_app_type] => 1 [patent_app_number] => 8/516830 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 11885 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623444.pdf [firstpage_image] =>[orig_patent_app_number] => 516830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516830
Electrically-erasable ROM with pulse-driven memory cell transistors Aug 17, 1995 Issued
Array ( [id] => 3858429 [patent_doc_number] => 05719815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle' [patent_app_type] => 1 [patent_app_number] => 8/503738 [patent_app_country] => US [patent_app_date] => 1995-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11809 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719815.pdf [firstpage_image] =>[orig_patent_app_number] => 503738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503738
Semiconductor memory having a refresh operation cycle and operating at a high speed and reduced power consumption in a normal operation cycle Jul 17, 1995 Issued
Array ( [id] => 3586960 [patent_doc_number] => 05524096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Circuit for generating a delayed standby signal in response to an external standby command' [patent_app_type] => 1 [patent_app_number] => 8/496436 [patent_app_country] => US [patent_app_date] => 1995-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5892 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524096.pdf [firstpage_image] =>[orig_patent_app_number] => 496436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/496436
Circuit for generating a delayed standby signal in response to an external standby command Jun 28, 1995 Issued
Array ( [id] => 3704638 [patent_doc_number] => 05596534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM' [patent_app_type] => 1 [patent_app_number] => 8/495338 [patent_app_country] => US [patent_app_date] => 1995-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3071 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596534.pdf [firstpage_image] =>[orig_patent_app_number] => 495338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/495338
Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM Jun 26, 1995 Issued
Array ( [id] => 3600408 [patent_doc_number] => 05586080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Local word line phase driver' [patent_app_type] => 1 [patent_app_number] => 8/494535 [patent_app_country] => US [patent_app_date] => 1995-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2786 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586080.pdf [firstpage_image] =>[orig_patent_app_number] => 494535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/494535
Local word line phase driver Jun 25, 1995 Issued
Array ( [id] => 3558226 [patent_doc_number] => 05555521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method of operating the semiconductor memory storing analog data and analog data storing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/489037 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11767 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555521.pdf [firstpage_image] =>[orig_patent_app_number] => 489037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489037
Method of operating the semiconductor memory storing analog data and analog data storing apparatus Jun 8, 1995 Issued
Array ( [id] => 3516432 [patent_doc_number] => 05570312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'SRAM cell using word line controlled pull-up NMOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/488705 [patent_app_country] => US [patent_app_date] => 1995-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1980 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570312.pdf [firstpage_image] =>[orig_patent_app_number] => 488705 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488705
SRAM cell using word line controlled pull-up NMOS transistors Jun 8, 1995 Issued
Array ( [id] => 3867077 [patent_doc_number] => 05768205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Process of transfering streams of data to and from a random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/483002 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6191 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768205.pdf [firstpage_image] =>[orig_patent_app_number] => 483002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483002
Process of transfering streams of data to and from a random access memory device Jun 6, 1995 Issued
Array ( [id] => 3659290 [patent_doc_number] => 05684753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Synchronous data transfer system' [patent_app_type] => 1 [patent_app_number] => 8/479297 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6195 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 511 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684753.pdf [firstpage_image] =>[orig_patent_app_number] => 479297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479297
Synchronous data transfer system Jun 6, 1995 Issued
Array ( [id] => 3704363 [patent_doc_number] => 05680358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'System transferring streams of data' [patent_app_type] => 1 [patent_app_number] => 8/480636 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6190 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680358.pdf [firstpage_image] =>[orig_patent_app_number] => 480636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480636
System transferring streams of data Jun 6, 1995 Issued
Array ( [id] => 3704504 [patent_doc_number] => 05680368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Dram system with control data' [patent_app_type] => 1 [patent_app_number] => 8/473586 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6191 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 514 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680368.pdf [firstpage_image] =>[orig_patent_app_number] => 473586 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/473586
Dram system with control data Jun 6, 1995 Issued
Array ( [id] => 3704490 [patent_doc_number] => 05680367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Process for controlling writing data to a DRAM array' [patent_app_type] => 1 [patent_app_number] => 8/480637 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6197 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680367.pdf [firstpage_image] =>[orig_patent_app_number] => 480637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/480637
Process for controlling writing data to a DRAM array Jun 6, 1995 Issued
Array ( [id] => 3704517 [patent_doc_number] => 05680369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Synchronous dynamic random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/474047 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6133 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680369.pdf [firstpage_image] =>[orig_patent_app_number] => 474047 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474047
Synchronous dynamic random access memory device Jun 6, 1995 Issued
Array ( [id] => 3703876 [patent_doc_number] => 05661692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Read/write dual port memory having an on-chip input data register' [patent_app_type] => 1 [patent_app_number] => 8/479321 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10286 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661692.pdf [firstpage_image] =>[orig_patent_app_number] => 479321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479321
Read/write dual port memory having an on-chip input data register Jun 6, 1995 Issued
Array ( [id] => 3630455 [patent_doc_number] => 05615151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Semiconductor integrated circuit operable and programmable at multiple voltage levels' [patent_app_type] => 1 [patent_app_number] => 8/478334 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 12180 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615151.pdf [firstpage_image] =>[orig_patent_app_number] => 478334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/478334
Semiconductor integrated circuit operable and programmable at multiple voltage levels Jun 6, 1995 Issued
Array ( [id] => 3704535 [patent_doc_number] => 05680370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Synchronous DRAM device having a control data buffer' [patent_app_type] => 1 [patent_app_number] => 8/486168 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 430 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680370.pdf [firstpage_image] =>[orig_patent_app_number] => 486168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486168
Synchronous DRAM device having a control data buffer Jun 6, 1995 Issued
Array ( [id] => 3892311 [patent_doc_number] => 05805518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data' [patent_app_type] => 1 [patent_app_number] => 8/483618 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6166 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805518.pdf [firstpage_image] =>[orig_patent_app_number] => 483618 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483618
Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data Jun 6, 1995 Issued
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