Search

Lee D Wilson

Examiner (ID: 175, Phone: (571)272-4499 , Office: P/3727 )

Most Active Art Unit
3723
Art Unit(s)
3203, 3723, 3727
Total Applications
4059
Issued Applications
3286
Pending Applications
170
Abandoned Applications
602

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3562489 [patent_doc_number] => 05493531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/350961 [patent_app_country] => US [patent_app_date] => 1994-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493531.pdf [firstpage_image] =>[orig_patent_app_number] => 350961 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/350961
Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device Dec 6, 1994 Issued
Array ( [id] => 3567012 [patent_doc_number] => 05502684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Semiconductor memory having high speed and low power data read/write circuit' [patent_app_type] => 1 [patent_app_number] => 8/351650 [patent_app_country] => US [patent_app_date] => 1994-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4109 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502684.pdf [firstpage_image] =>[orig_patent_app_number] => 351650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/351650
Semiconductor memory having high speed and low power data read/write circuit Dec 6, 1994 Issued
Array ( [id] => 3536359 [patent_doc_number] => 05528544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Semiconductor memory device having high speed sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/351642 [patent_app_country] => US [patent_app_date] => 1994-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4813 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528544.pdf [firstpage_image] =>[orig_patent_app_number] => 351642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/351642
Semiconductor memory device having high speed sense amplifier Dec 6, 1994 Issued
Array ( [id] => 3558102 [patent_doc_number] => 05546346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/354124 [patent_app_country] => US [patent_app_date] => 1994-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 12580 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546346.pdf [firstpage_image] =>[orig_patent_app_number] => 354124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354124
Semiconductor memory device Dec 5, 1994 Issued
Array ( [id] => 3502393 [patent_doc_number] => 05537362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Low-voltage EEPROM using charge-pumped word lines' [patent_app_type] => 1 [patent_app_number] => 8/349930 [patent_app_country] => US [patent_app_date] => 1994-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5324 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537362.pdf [firstpage_image] =>[orig_patent_app_number] => 349930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/349930
Low-voltage EEPROM using charge-pumped word lines Dec 5, 1994 Issued
Array ( [id] => 3590392 [patent_doc_number] => 05499217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Bias circuit for a memory line decoder driver of nonvolatile memories' [patent_app_type] => 1 [patent_app_number] => 8/348461 [patent_app_country] => US [patent_app_date] => 1994-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2508 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499217.pdf [firstpage_image] =>[orig_patent_app_number] => 348461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348461
Bias circuit for a memory line decoder driver of nonvolatile memories Dec 1, 1994 Issued
Array ( [id] => 3507690 [patent_doc_number] => 05532967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Method for suppressing peak current in a video RAM and in a serial access memory block' [patent_app_type] => 1 [patent_app_number] => 8/352735 [patent_app_country] => US [patent_app_date] => 1994-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2192 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532967.pdf [firstpage_image] =>[orig_patent_app_number] => 352735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352735
Method for suppressing peak current in a video RAM and in a serial access memory block Dec 1, 1994 Issued
08/353231 MEMORY CELL AND A MEMORY DEVICE HAVING REDUCED SOFT ERROR Dec 1, 1994 Abandoned
Array ( [id] => 3523533 [patent_doc_number] => 05513148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Synchronous NAND DRAM architecture' [patent_app_type] => 1 [patent_app_number] => 8/348552 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3214 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513148.pdf [firstpage_image] =>[orig_patent_app_number] => 348552 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348552
Synchronous NAND DRAM architecture Nov 30, 1994 Issued
Array ( [id] => 3623468 [patent_doc_number] => 05535168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Method and apparatus for selectively erasing memory to extend battery life' [patent_app_type] => 1 [patent_app_number] => 8/347751 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535168.pdf [firstpage_image] =>[orig_patent_app_number] => 347751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347751
Method and apparatus for selectively erasing memory to extend battery life Nov 30, 1994 Issued
Array ( [id] => 3546921 [patent_doc_number] => 05495450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method and assembly for mounting an electronic device having an optically erasable surface' [patent_app_type] => 1 [patent_app_number] => 8/345035 [patent_app_country] => US [patent_app_date] => 1994-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2096 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495450.pdf [firstpage_image] =>[orig_patent_app_number] => 345035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/345035
Method and assembly for mounting an electronic device having an optically erasable surface Nov 24, 1994 Issued
Array ( [id] => 3520789 [patent_doc_number] => 05563820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Semiconductor memory device having two layers of bit lines arranged crossing with each other' [patent_app_type] => 1 [patent_app_number] => 8/347092 [patent_app_country] => US [patent_app_date] => 1994-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7366 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563820.pdf [firstpage_image] =>[orig_patent_app_number] => 347092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347092
Semiconductor memory device having two layers of bit lines arranged crossing with each other Nov 22, 1994 Issued
Array ( [id] => 3502355 [patent_doc_number] => 05537359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Memory device' [patent_app_type] => 1 [patent_app_number] => 8/343111 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5071 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537359.pdf [firstpage_image] =>[orig_patent_app_number] => 343111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343111
Memory device Nov 21, 1994 Issued
Array ( [id] => 3114407 [patent_doc_number] => 05448529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'High speed and hierarchical address transition detection circuit' [patent_app_type] => 1 [patent_app_number] => 8/341392 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2558 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448529.pdf [firstpage_image] =>[orig_patent_app_number] => 341392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341392
High speed and hierarchical address transition detection circuit Nov 16, 1994 Issued
Array ( [id] => 3563649 [patent_doc_number] => 05519662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/339611 [patent_app_country] => US [patent_app_date] => 1994-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6929 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519662.pdf [firstpage_image] =>[orig_patent_app_number] => 339611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339611
Semiconductor memory device Nov 14, 1994 Issued
Array ( [id] => 3546709 [patent_doc_number] => 05495435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Synchronous DRAM memory module' [patent_app_type] => 1 [patent_app_number] => 8/339730 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2749 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495435.pdf [firstpage_image] =>[orig_patent_app_number] => 339730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339730
Synchronous DRAM memory module Nov 13, 1994 Issued
Array ( [id] => 3563686 [patent_doc_number] => 05519665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Semiconductor memory device having word line driver requiring single word line drive signal' [patent_app_type] => 1 [patent_app_number] => 8/336192 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5090 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519665.pdf [firstpage_image] =>[orig_patent_app_number] => 336192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/336192
Semiconductor memory device having word line driver requiring single word line drive signal Nov 3, 1994 Issued
Array ( [id] => 3633062 [patent_doc_number] => 05594698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Random access memory (RAM) based configurable arrays' [patent_app_type] => 1 [patent_app_number] => 8/334885 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 13104 [patent_no_of_claims] => 159 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594698.pdf [firstpage_image] =>[orig_patent_app_number] => 334885 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334885
Random access memory (RAM) based configurable arrays Nov 3, 1994 Issued
Array ( [id] => 4077870 [patent_doc_number] => 05867446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/332626 [patent_app_country] => US [patent_app_date] => 1994-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 24 [patent_no_of_words] => 40537 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867446.pdf [firstpage_image] =>[orig_patent_app_number] => 332626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/332626
Synchronous semiconductor memory device Oct 30, 1994 Issued
Array ( [id] => 3574291 [patent_doc_number] => 05483486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Charge pump circuit for providing multiple output voltages for flash memory' [patent_app_type] => 1 [patent_app_number] => 8/326654 [patent_app_country] => US [patent_app_date] => 1994-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 15225 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483486.pdf [firstpage_image] =>[orig_patent_app_number] => 326654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/326654
Charge pump circuit for providing multiple output voltages for flash memory Oct 18, 1994 Issued
Menu