Search

Lee S Cohen

Examiner (ID: 13979, Phone: (571)272-4763 , Office: P/3739 )

Most Active Art Unit
3739
Art Unit(s)
3739, 3794, 3305, 3311, 3736, 0
Total Applications
3720
Issued Applications
3006
Pending Applications
173
Abandoned Applications
543

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17985981 [patent_doc_number] => 20220352018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/446215 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446215
CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE Aug 26, 2021 Pending
Array ( [id] => 18230060 [patent_doc_number] => 20230069054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH MULTI-LAYER EPITAXY AND LAYER TRANSFER [patent_app_type] => utility [patent_app_number] => 17/410257 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410257
GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH MULTI-LAYER EPITAXY AND LAYER TRANSFER Aug 23, 2021 Abandoned
Array ( [id] => 18212567 [patent_doc_number] => 20230058831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MOLECULAR LAYER DEPOSITION LINER FOR 3D NAND [patent_app_type] => utility [patent_app_number] => 17/407533 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407533
MOLECULAR LAYER DEPOSITION LINER FOR 3D NAND Aug 19, 2021 Pending
Array ( [id] => 17417031 [patent_doc_number] => 20220051935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SUBSTRATE PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/399049 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399049
Substrate processing method Aug 10, 2021 Issued
Array ( [id] => 17247400 [patent_doc_number] => 20210367145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SEMICONDUCTOR STRUCTURE, ELECTRODE STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/392927 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392927
Semiconductor structure, electrode structure and method of forming the same Aug 2, 2021 Issued
Array ( [id] => 18225574 [patent_doc_number] => 20230064568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/603450 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/603450
Method of making a metal silicide contact to a silicon substrate Jul 28, 2021 Issued
Array ( [id] => 18593304 [patent_doc_number] => 11742215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Methods for forming a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/386699 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9684 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386699
Methods for forming a semiconductor device Jul 27, 2021 Issued
Array ( [id] => 18649595 [patent_doc_number] => 20230295412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => LOW CEILING TEMPERATURE HOMOPOLYMERS AS SACRIFICIAL PROTECTION LAYERS FOR ENVIRONMENTALLY SENSITIVE SUBSTRATES [patent_app_type] => utility [patent_app_number] => 18/006552 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18006552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/006552
LOW CEILING TEMPERATURE HOMOPOLYMERS AS SACRIFICIAL PROTECTION LAYERS FOR ENVIRONMENTALLY SENSITIVE SUBSTRATES Jul 22, 2021 Pending
Array ( [id] => 18743375 [patent_doc_number] => 20230352363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => COMPOSITE MATERIAL, HEAT SPREADER AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/017970 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18017970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/017970
COMPOSITE MATERIAL, HEAT SPREADER AND SEMICONDUCTOR PACKAGE Jul 12, 2021 Pending
Array ( [id] => 18402264 [patent_doc_number] => 11664415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Method of making interconnect structure having ferroelectric capacitors exhibiting negative capacitance [patent_app_type] => utility [patent_app_number] => 17/373586 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373586
Method of making interconnect structure having ferroelectric capacitors exhibiting negative capacitance Jul 11, 2021 Issued
Array ( [id] => 18562996 [patent_doc_number] => 11728249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor package and method [patent_app_type] => utility [patent_app_number] => 17/373063 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373063
Semiconductor package and method Jul 11, 2021 Issued
Array ( [id] => 18068114 [patent_doc_number] => 20220399202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/368055 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368055
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 5, 2021 Abandoned
Array ( [id] => 18528721 [patent_doc_number] => 11715725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor device assemblies with electrically functional heat transfer structures [patent_app_type] => utility [patent_app_number] => 17/364844 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364844
Semiconductor device assemblies with electrically functional heat transfer structures Jun 29, 2021 Issued
Array ( [id] => 18967521 [patent_doc_number] => 11901302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => InFO-POP structures with TIVs having cavities [patent_app_type] => utility [patent_app_number] => 17/360313 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 37 [patent_no_of_words] => 8330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360313
InFO-POP structures with TIVs having cavities Jun 27, 2021 Issued
Array ( [id] => 17318753 [patent_doc_number] => 20210407803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => MANUFACTURING METHOD OF PHOTOMASK, AND PHOTOMASK BLANK [patent_app_type] => utility [patent_app_number] => 17/354201 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354201
Manufacturing method of photomask, and photomask blank Jun 21, 2021 Issued
Array ( [id] => 18437416 [patent_doc_number] => 20230184711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DEVICES WITH FIELD EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/003493 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18003493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/003493
Devices with field effect transistors Jun 17, 2021 Issued
Array ( [id] => 19945565 [patent_doc_number] => 12317717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 17/755281 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 10242 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17755281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/755281
Display panel and display device May 17, 2021 Issued
Array ( [id] => 17070832 [patent_doc_number] => 20210273049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => Isolation Features and Methods of Fabricating the Same [patent_app_type] => utility [patent_app_number] => 17/322087 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322087
Isolation features and methods of fabricating the same May 16, 2021 Issued
Array ( [id] => 17993295 [patent_doc_number] => 20220359332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => TEMPORARY PASSIVATION LAYER ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/315342 [patent_app_country] => US [patent_app_date] => 2021-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315342
TEMPORARY PASSIVATION LAYER ON A SUBSTRATE May 8, 2021 Pending
Array ( [id] => 18900521 [patent_doc_number] => 20240016006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SUPPORTING BACKPLANE AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/763215 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17763215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/763215
Display panel and manufacturing method therefor, and display apparatus May 7, 2021 Issued
Menu