Search

Leigh M. Garbowski

Examiner (ID: 10350, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2304, 2825, 2851, 2764, 2763, 2768
Total Applications
1698
Issued Applications
1522
Pending Applications
72
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19864113 [patent_doc_number] => 20250102899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MASK OPTIMIZATION PREFERENTIALLY ACCOUNTING FOR OVERLAP REGIONS [patent_app_type] => utility [patent_app_number] => 18/814430 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814430
MASK OPTIMIZATION PREFERENTIALLY ACCOUNTING FOR OVERLAP REGIONS Aug 22, 2024 Pending
Array ( [id] => 19802892 [patent_doc_number] => 20250068817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => VARIATION TRIMMING FOR RE-PROGRAMMABLE AND/OR RECONFIGURABLE ANALOG CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/808188 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808188
Variation trimming for re-programmable and/or reconfigurable analog circuitry Aug 18, 2024 Issued
Array ( [id] => 19885955 [patent_doc_number] => 12271672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Deterministic parallel routing approach for accelerating pathfinder-based algorithms [patent_app_type] => utility [patent_app_number] => 18/804644 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7591 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804644
Deterministic parallel routing approach for accelerating pathfinder-based algorithms Aug 13, 2024 Issued
Array ( [id] => 19499493 [patent_doc_number] => 20240338511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING SAME AND A SYSTEM [patent_app_type] => utility [patent_app_number] => 18/746888 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746888 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746888
Integrated circuit and method of forming same and a system Jun 17, 2024 Issued
Array ( [id] => 20131308 [patent_doc_number] => 12373621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Verification of hardware design for data transformation component [patent_app_type] => utility [patent_app_number] => 18/675048 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675048
Verification of hardware design for data transformation component May 26, 2024 Issued
Array ( [id] => 20203350 [patent_doc_number] => 12406130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Geometric mask rule check with favorable and unfavorable zones [patent_app_type] => utility [patent_app_number] => 18/672836 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672836
Geometric mask rule check with favorable and unfavorable zones May 22, 2024 Issued
Array ( [id] => 19434911 [patent_doc_number] => 20240303409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => AUTOMATED SYSTEM AND METHOD FOR CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/669864 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669864
Automated system and method for circuit design May 20, 2024 Issued
Array ( [id] => 19971549 [patent_doc_number] => 12340164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Methods and systems for reticle enhancement technology of a design pattern to be manufactured on a substrate [patent_app_type] => utility [patent_app_number] => 18/657435 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657435
Methods and systems for reticle enhancement technology of a design pattern to be manufactured on a substrate May 6, 2024 Issued
Array ( [id] => 19979293 [patent_doc_number] => 12346770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Variational quantum state preparation [patent_app_type] => utility [patent_app_number] => 18/653705 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653705
Variational quantum state preparation May 1, 2024 Issued
Array ( [id] => 19587974 [patent_doc_number] => 20240385531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METROLOGY METHOD AND APPARATUS, COMPUTER PROGRAM AND LITHOGRAPHIC SYSTEM [patent_app_type] => utility [patent_app_number] => 18/639905 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639905
METROLOGY METHOD AND APPARATUS, COMPUTER PROGRAM AND LITHOGRAPHIC SYSTEM Apr 17, 2024 Pending
Array ( [id] => 20221274 [patent_doc_number] => 20250284205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => ROBUST AND ACCURATE OVERLAY TARGET DESIGN FOR CMP [patent_app_type] => utility [patent_app_number] => 18/636859 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636859
Robust and accurate overlay target design for CMP Apr 15, 2024 Issued
Array ( [id] => 19716663 [patent_doc_number] => 12202183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-21 [patent_title] => Apparatus and method for instantaneous generation of a pin placement quote in an injection molding process [patent_app_type] => utility [patent_app_number] => 18/615880 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 26851 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615880
Apparatus and method for instantaneous generation of a pin placement quote in an injection molding process Mar 24, 2024 Issued
Array ( [id] => 19443348 [patent_doc_number] => 12093616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-17 [patent_title] => Method and system for ship stability prediction by weighted fusion of radial basis function neural network and random forest based on gradient descent [patent_app_type] => utility [patent_app_number] => 18/585089 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4996 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/585089
Method and system for ship stability prediction by weighted fusion of radial basis function neural network and random forest based on gradient descent Feb 22, 2024 Issued
Array ( [id] => 19933977 [patent_doc_number] => 12307182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Voltage impacts on delays for timing simulation [patent_app_type] => utility [patent_app_number] => 18/439639 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439639
Voltage impacts on delays for timing simulation Feb 11, 2024 Issued
Array ( [id] => 19506863 [patent_doc_number] => 12118285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => Systems and methods for analog integrated circuits (IC) design using quantum evolution algorithms (QEAs) [patent_app_type] => utility [patent_app_number] => 18/418454 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418454
Systems and methods for analog integrated circuits (IC) design using quantum evolution algorithms (QEAs) Jan 21, 2024 Issued
Array ( [id] => 19159972 [patent_doc_number] => 20240152679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => Integrated Circuit Layout Validation Using Machine Learning [patent_app_type] => utility [patent_app_number] => 18/415245 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415245
Integrated circuit layout validation using machine learning Jan 16, 2024 Issued
Array ( [id] => 19971543 [patent_doc_number] => 12340158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Circuit synthesis optimization for implements on integrated circuit [patent_app_type] => utility [patent_app_number] => 18/403924 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403924
Circuit synthesis optimization for implements on integrated circuit Jan 3, 2024 Issued
Array ( [id] => 19732811 [patent_doc_number] => 12210809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Methods and systems for printed circuit board component placement and approval [patent_app_type] => utility [patent_app_number] => 18/399429 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20701 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399429 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399429
Methods and systems for printed circuit board component placement and approval Dec 27, 2023 Issued
Array ( [id] => 19956658 [patent_doc_number] => 12327073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Methods and systems for printed circuit board component placement and approval [patent_app_type] => utility [patent_app_number] => 18/399421 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14844 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399421
Methods and systems for printed circuit board component placement and approval Dec 27, 2023 Issued
Array ( [id] => 19740140 [patent_doc_number] => 12216975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Methods and systems for printed circuit board component placement and approval [patent_app_type] => utility [patent_app_number] => 18/399436 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20701 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399436
Methods and systems for printed circuit board component placement and approval Dec 27, 2023 Issued
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