Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19537783 [patent_doc_number] => 12130334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => State of health determination of a battery [patent_app_type] => utility [patent_app_number] => 17/379246 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17379246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/379246
State of health determination of a battery Jul 18, 2021 Issued
Array ( [id] => 18386424 [patent_doc_number] => 11657207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Wafer sensitivity determination and communication [patent_app_type] => utility [patent_app_number] => 17/378423 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/378423
Wafer sensitivity determination and communication Jul 15, 2021 Issued
Array ( [id] => 20914451 [patent_doc_number] => 12711299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Systems and methods for determining specification limits in a semiconductor device virtual fabrication environment [patent_app_type] => utility [patent_app_number] => 18/015855 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18015855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/015855
SYSTEMS AND METHODS FOR DETERMINING SPECIFICATION LIMITS IN A SEMICONDUCTOR DEVICE VIRTUAL FABRICATION ENVIRONMENT Jul 13, 2021 Pending
Array ( [id] => 19582960 [patent_doc_number] => 12149092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Information handling system housing integrated wireless charging coil in housing bottom side [patent_app_type] => utility [patent_app_number] => 17/372755 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 3742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372755
Information handling system housing integrated wireless charging coil in housing bottom side Jul 11, 2021 Issued
Array ( [id] => 17187565 [patent_doc_number] => 20210334450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SYSTEMS AND METHODS FOR IMPLEMENTING TILE-LEVEL PREDICATION WITHIN A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/365555 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365555
SYSTEMS AND METHODS FOR IMPLEMENTING TILE-LEVEL PREDICATION WITHIN A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT Jun 30, 2021 Abandoned
Array ( [id] => 18174396 [patent_doc_number] => 11574108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Block level design method for heterogeneous PG-structure cells [patent_app_type] => utility [patent_app_number] => 17/363669 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363669
Block level design method for heterogeneous PG-structure cells Jun 29, 2021 Issued
Array ( [id] => 18104546 [patent_doc_number] => 11544436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Hardware-software interaction testing using formal verification [patent_app_type] => utility [patent_app_number] => 17/353715 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353715
Hardware-software interaction testing using formal verification Jun 20, 2021 Issued
Array ( [id] => 18015422 [patent_doc_number] => 11507720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Systems and methods for signal observability rating [patent_app_type] => utility [patent_app_number] => 17/345857 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11987 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345857
Systems and methods for signal observability rating Jun 10, 2021 Issued
Array ( [id] => 17114356 [patent_doc_number] => 20210294953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => Systems And Methods For Logic Circuit Replacement With Configurable Circuits [patent_app_type] => utility [patent_app_number] => 17/337824 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337824 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337824
Systems and methods for logic circuit replacement with configurable circuits Jun 2, 2021 Issued
Array ( [id] => 18728237 [patent_doc_number] => 20230342530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => LEARNING APPARATUS, INFERENCE APPARATUS, AND PROGRAMMABLE LOGIC DEVICE DEVELOPMENT TOOLCHAIN [patent_app_type] => utility [patent_app_number] => 17/920848 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17920848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/920848
Learning apparatus, inference apparatus, and programmable logic device development toolchain May 31, 2021 Issued
Array ( [id] => 17558202 [patent_doc_number] => 11314911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => High-level synthesis implementation of data structures in hardware [patent_app_type] => utility [patent_app_number] => 17/331835 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331835
High-level synthesis implementation of data structures in hardware May 26, 2021 Issued
Array ( [id] => 18038730 [patent_doc_number] => 20220382946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => AUTOMATED SYSTEM AND METHOD FOR CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/331825 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331825
Automated system and method for circuit design May 26, 2021 Issued
Array ( [id] => 17940746 [patent_doc_number] => 11475202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Method of designing a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/323893 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2115 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323893
Method of designing a semiconductor device May 17, 2021 Issued
Array ( [id] => 18437892 [patent_doc_number] => 20230185187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => VERIFYING FREEFORM CURVILINEAR FEATURES OF A MASK DESIGN [patent_app_type] => utility [patent_app_number] => 17/924543 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17924543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/924543
VERIFYING FREEFORM CURVILINEAR FEATURES OF A MASK DESIGN May 12, 2021 Pending
Array ( [id] => 18007520 [patent_doc_number] => 20220366286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ENTITY STEERING OF A RUNNING QUANTUM PROGRAM [patent_app_type] => utility [patent_app_number] => 17/319504 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319504
Entity steering of a running quantum program May 12, 2021 Issued
Array ( [id] => 18422781 [patent_doc_number] => 20230177245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SYSTEM, METHOD, COMPUTER-ACCESSIBLE MEDIUM, AND CIRCUIT FOR CRIPPLING THE ORACLE IN LOGIC LOCKING [patent_app_type] => utility [patent_app_number] => 17/923674 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17923674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/923674
System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking May 6, 2021 Issued
Array ( [id] => 18303621 [patent_doc_number] => 11625525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-11 [patent_title] => Grouping cells in cell library based on clustering [patent_app_type] => utility [patent_app_number] => 17/314942 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314942
Grouping cells in cell library based on clustering May 6, 2021 Issued
Array ( [id] => 17771506 [patent_doc_number] => 11403449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Systems and methods for configurable switches for verification IP [patent_app_type] => utility [patent_app_number] => 17/246268 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246268
Systems and methods for configurable switches for verification IP Apr 29, 2021 Issued
Array ( [id] => 17026017 [patent_doc_number] => 20210249889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => Wireless Charging Receiving Apparatus, Method, Terminal, and System [patent_app_type] => utility [patent_app_number] => 17/244017 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244017
Wireless charging receiving apparatus, method, terminal, and system Apr 28, 2021 Issued
Array ( [id] => 17771505 [patent_doc_number] => 11403448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Apparatus and method for mapping foundational components during design porting from one process technology to another process technology [patent_app_type] => utility [patent_app_number] => 17/239000 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239000
Apparatus and method for mapping foundational components during design porting from one process technology to another process technology Apr 22, 2021 Issued
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