Search

Leigh M. Garbowski

Examiner (ID: 10350, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2304, 2825, 2851, 2764, 2763, 2768
Total Applications
1698
Issued Applications
1522
Pending Applications
72
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18527950 [patent_doc_number] => 11714944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Optimization of physical cell placement for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/139016 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9310 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139016
Optimization of physical cell placement for integrated circuits Dec 30, 2020 Issued
Array ( [id] => 17710022 [patent_doc_number] => 20220210030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SYNTHESIS OF A NETWORK-ON-CHIP (NoC) USING PERFORMANCE CONSTRAINTS AND OBJECTIVES [patent_app_type] => utility [patent_app_number] => 17/138839 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138839
Synthesis of a network-on-chip (NoC) using performance constraints and objectives Dec 29, 2020 Issued
Array ( [id] => 17622245 [patent_doc_number] => 11341302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Method for translation of analog circuit netlist to a digital model and elimination of zero delay loops within the digital model [patent_app_type] => utility [patent_app_number] => 17/130429 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 17183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130429
Method for translation of analog circuit netlist to a digital model and elimination of zero delay loops within the digital model Dec 21, 2020 Issued
Array ( [id] => 17637202 [patent_doc_number] => 11347926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Optical mode optimization for wafer inspection [patent_app_type] => utility [patent_app_number] => 17/121174 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121174
Optical mode optimization for wafer inspection Dec 13, 2020 Issued
Array ( [id] => 18415123 [patent_doc_number] => 11669666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Methods relating to circuit verification [patent_app_type] => utility [patent_app_number] => 17/106965 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 10985 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106965
Methods relating to circuit verification Nov 29, 2020 Issued
Array ( [id] => 18009404 [patent_doc_number] => 20220368171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND DEVICES FOR PROVIDING OPERATIONAL FEEDBACK DURING POWER TRANSFER IN A WIRELESS POWER TRANSFER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/285505 [patent_app_country] => US [patent_app_date] => 2020-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17285505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/285505
Method and devices for providing operational feedback during power transfer in a wireless power transfer system Nov 25, 2020 Issued
Array ( [id] => 18183760 [patent_doc_number] => 20230044490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => METHOD FOR IMPROVING CONSISTENCY IN MASK PATTERN GENERATION [patent_app_type] => utility [patent_app_number] => 17/782741 [patent_app_country] => US [patent_app_date] => 2020-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/782741
METHOD FOR IMPROVING CONSISTENCY IN MASK PATTERN GENERATION Nov 20, 2020 Pending
Array ( [id] => 17352449 [patent_doc_number] => 11227088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Method for simulating semiconductor device [patent_app_type] => utility [patent_app_number] => 16/951351 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7192 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951351
Method for simulating semiconductor device Nov 17, 2020 Issued
Array ( [id] => 16676045 [patent_doc_number] => 20210064811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION [patent_app_type] => utility [patent_app_number] => 17/097106 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097106
Three-dimensional mask model for photolithography simulation Nov 12, 2020 Issued
Array ( [id] => 18053259 [patent_doc_number] => 11526644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Controlling test networks of chips using integrated processors [patent_app_type] => utility [patent_app_number] => 17/089864 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089864
Controlling test networks of chips using integrated processors Nov 4, 2020 Issued
Array ( [id] => 17499722 [patent_doc_number] => 11288428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Integrated circuit design modification for localization of scan chain defects [patent_app_type] => utility [patent_app_number] => 17/085830 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085830
Integrated circuit design modification for localization of scan chain defects Oct 29, 2020 Issued
Array ( [id] => 17409310 [patent_doc_number] => 11250197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Channel less floor-planning in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/079727 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7245 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079727 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079727
Channel less floor-planning in integrated circuits Oct 25, 2020 Issued
Array ( [id] => 18471676 [patent_doc_number] => 20230205962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => AUTOMATIC LAYOUT METHOD FOR PAD RING USED FOR OPTIMIZING ELECTROSTATIC DISCHARGING CAPACITY OF CHIP [patent_app_type] => utility [patent_app_number] => 17/595632 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 732 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/595632
Automatic layout method for pad ring used for optimizing electrostatic discharging capacity of chip Oct 25, 2020 Issued
Array ( [id] => 17564902 [patent_doc_number] => 20220129051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => PASSIVELY COOLING HARDWARE COMPONENTS [patent_app_type] => utility [patent_app_number] => 17/077361 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077361
Passively cooling hardware components Oct 21, 2020 Issued
Array ( [id] => 17550456 [patent_doc_number] => 20220121798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Circuit Synthesis Optimization for Implements on Integrated Circuit [patent_app_type] => utility [patent_app_number] => 17/075760 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075760
Circuit synthesis optimization for implements on integrated circuit Oct 20, 2020 Issued
Array ( [id] => 17528916 [patent_doc_number] => 11301605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => System and method of prototyping virtual circuits with physical proxies [patent_app_type] => utility [patent_app_number] => 17/072763 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072763
System and method of prototyping virtual circuits with physical proxies Oct 15, 2020 Issued
Array ( [id] => 17380187 [patent_doc_number] => 11238204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Transmitter test with interpolation [patent_app_type] => utility [patent_app_number] => 17/066284 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066284
Transmitter test with interpolation Oct 7, 2020 Issued
Array ( [id] => 16987206 [patent_doc_number] => 11074381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Verification of hardware design for data transformation component [patent_app_type] => utility [patent_app_number] => 17/065678 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065678 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065678
Verification of hardware design for data transformation component Oct 7, 2020 Issued
Array ( [id] => 17901398 [patent_doc_number] => 20220311060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SMART BATTERY [patent_app_type] => utility [patent_app_number] => 17/297345 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17297345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/297345
Smart battery Sep 27, 2020 Issued
Array ( [id] => 17009740 [patent_doc_number] => 20210240901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => CELL ROW ARRANGEMENT IN REGIONS OF INTEGRATED CIRCUIT LAYOUT [patent_app_type] => utility [patent_app_number] => 17/025296 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025296
Cell row arrangement in regions of integrated circuit layout Sep 17, 2020 Issued
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