Search

Leigh M. Garbowski

Examiner (ID: 10350, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2304, 2825, 2851, 2764, 2763, 2768
Total Applications
1698
Issued Applications
1522
Pending Applications
72
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17106555 [patent_doc_number] => 11126773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Method for paralleled SiC power switching devices based on wiring optimization [patent_app_type] => utility [patent_app_number] => 17/024894 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2334 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/024894
Method for paralleled SiC power switching devices based on wiring optimization Sep 17, 2020 Issued
Array ( [id] => 17180428 [patent_doc_number] => 11157672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-26 [patent_title] => System and method for determining hybrid-manufacturing process plans for integrated circuits based on satisfiability modulo difference logic solver [patent_app_type] => utility [patent_app_number] => 17/023747 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023747
System and method for determining hybrid-manufacturing process plans for integrated circuits based on satisfiability modulo difference logic solver Sep 16, 2020 Issued
Array ( [id] => 17331691 [patent_doc_number] => 11222155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => Method and apparatus for reducing pessimism of graph based static timing analysis [patent_app_type] => utility [patent_app_number] => 17/021938 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14997 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021938
Method and apparatus for reducing pessimism of graph based static timing analysis Sep 14, 2020 Issued
Array ( [id] => 18276282 [patent_doc_number] => 11615226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Recording medium, computing method, and computing device [patent_app_type] => utility [patent_app_number] => 17/017814 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4543 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017814
Recording medium, computing method, and computing device Sep 10, 2020 Issued
Array ( [id] => 18119586 [patent_doc_number] => 11550981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Distributed application processing with synchronization protocol [patent_app_type] => utility [patent_app_number] => 17/007980 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007980
Distributed application processing with synchronization protocol Aug 30, 2020 Issued
Array ( [id] => 18660162 [patent_doc_number] => 20230306169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits [patent_app_type] => utility [patent_app_number] => 18/041136 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18041136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/041136
Hybrid Switching Architecture For SerDes Communication Channels In Reconfigurable Hardware Modeling Circuits Aug 19, 2020 Pending
Array ( [id] => 17223807 [patent_doc_number] => 11176309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-16 [patent_title] => System and method for validation of photonics device layout designs [patent_app_type] => utility [patent_app_number] => 16/994830 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994830 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994830
System and method for validation of photonics device layout designs Aug 16, 2020 Issued
Array ( [id] => 17106564 [patent_doc_number] => 11126782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Applying reticle enhancement technique recipes based on failure modes predicted by an artificial neural network [patent_app_type] => utility [patent_app_number] => 16/989631 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989631
Applying reticle enhancement technique recipes based on failure modes predicted by an artificial neural network Aug 9, 2020 Issued
Array ( [id] => 16745454 [patent_doc_number] => 10970444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Methods and systems to verify correctness of bug fixes in integrated circuits [patent_app_type] => utility [patent_app_number] => 16/989347 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 14440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989347
Methods and systems to verify correctness of bug fixes in integrated circuits Aug 9, 2020 Issued
Array ( [id] => 16542840 [patent_doc_number] => 20200409255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => METHOD AND DEVICE FOR SUPERIMPOSING AT LEAST TWO IMAGES OF A PHOTOLITHOGRAPHIC MASK [patent_app_type] => utility [patent_app_number] => 16/912914 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912914
Method and device for superimposing at least two images of a photolithographic mask Jun 25, 2020 Issued
Array ( [id] => 17288485 [patent_doc_number] => 11205035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Bump connection placement in quantum devices in a flip chip configuration [patent_app_type] => utility [patent_app_number] => 16/909542 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909542
Bump connection placement in quantum devices in a flip chip configuration Jun 22, 2020 Issued
Array ( [id] => 18122187 [patent_doc_number] => 11553597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Three-dimensional light emitting appliance [patent_app_type] => utility [patent_app_number] => 16/909727 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3628 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909727
Three-dimensional light emitting appliance Jun 22, 2020 Issued
Array ( [id] => 16346682 [patent_doc_number] => 20200311333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING ANCHOR NODES AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 16/902846 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902846
Standard cell and semiconductor device including anchor nodes and method of making Jun 15, 2020 Issued
Array ( [id] => 17047084 [patent_doc_number] => 11100266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Generating integrated circuit floorplans using neural networks [patent_app_type] => utility [patent_app_number] => 16/889130 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7472 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889130
Generating integrated circuit floorplans using neural networks May 31, 2020 Issued
Array ( [id] => 19942516 [patent_doc_number] => 12314648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Remote programming systems and methods for programmable logic devices [patent_app_type] => utility [patent_app_number] => 17/614316 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17614316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/614316
Remote programming systems and methods for programmable logic devices May 27, 2020 Issued
Array ( [id] => 17744672 [patent_doc_number] => 11392743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Multiplexer [patent_app_type] => utility [patent_app_number] => 16/883524 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883524
Multiplexer May 25, 2020 Issued
Array ( [id] => 18912122 [patent_doc_number] => 11875101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Method for patterning process modelling [patent_app_type] => utility [patent_app_number] => 17/616368 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 19182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17616368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/616368
Method for patterning process modelling May 24, 2020 Issued
Array ( [id] => 17121350 [patent_doc_number] => 11132486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Systems and methods for multi-bit memory with embedded logic [patent_app_type] => utility [patent_app_number] => 16/879871 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879871
Systems and methods for multi-bit memory with embedded logic May 20, 2020 Issued
Array ( [id] => 16943216 [patent_doc_number] => 11055460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Input-directed constrained random simulation [patent_app_type] => utility [patent_app_number] => 16/880311 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880311
Input-directed constrained random simulation May 20, 2020 Issued
Array ( [id] => 16943223 [patent_doc_number] => 11055467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Method and apparatus for performing power mesh optimization with aid of additional wires [patent_app_type] => utility [patent_app_number] => 16/876151 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4655 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876151
Method and apparatus for performing power mesh optimization with aid of additional wires May 17, 2020 Issued
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