Leigh M. Garbowski

Array ( [id] => 17515901 [patent_doc_number] => 11295056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Vertex-based OPC for opening patterning [patent_app_type] => utility [patent_app_number] => 17/144975 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 12232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17017425 [patent_doc_number] => 11087067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit [patent_app_type] => utility [patent_app_number] => 17/142314 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13941 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16950587 [patent_doc_number] => 20210209279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => CONVERGENCE CENTRIC COVERAGE FOR CLOCK DOMAIN CROSSING (CDC) JITTER IN SIMULATION [patent_app_type] => utility [patent_app_number] => 17/139915 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20528647 [patent_doc_number] => 12547082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Combining physical modeling and machine learning [patent_app_type] => utility [patent_app_number] => 17/758398 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1947 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17758398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18527950 [patent_doc_number] => 11714944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Optimization of physical cell placement for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/139016 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9310 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17710022 [patent_doc_number] => 20220210030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SYNTHESIS OF A NETWORK-ON-CHIP (NoC) USING PERFORMANCE CONSTRAINTS AND OBJECTIVES [patent_app_type] => utility [patent_app_number] => 17/138839 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17622245 [patent_doc_number] => 11341302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Method for translation of analog circuit netlist to a digital model and elimination of zero delay loops within the digital model [patent_app_type] => utility [patent_app_number] => 17/130429 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 17183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17637202 [patent_doc_number] => 11347926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Optical mode optimization for wafer inspection [patent_app_type] => utility [patent_app_number] => 17/121174 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18415123 [patent_doc_number] => 11669666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Methods relating to circuit verification [patent_app_type] => utility [patent_app_number] => 17/106965 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 10985 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18009404 [patent_doc_number] => 20220368171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND DEVICES FOR PROVIDING OPERATIONAL FEEDBACK DURING POWER TRANSFER IN A WIRELESS POWER TRANSFER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/285505 [patent_app_country] => US [patent_app_date] => 2020-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17285505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18183760 [patent_doc_number] => 20230044490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => METHOD FOR IMPROVING CONSISTENCY IN MASK PATTERN GENERATION [patent_app_type] => utility [patent_app_number] => 17/782741 [patent_app_country] => US [patent_app_date] => 2020-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17352449 [patent_doc_number] => 11227088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Method for simulating semiconductor device [patent_app_type] => utility [patent_app_number] => 16/951351 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7192 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16676045 [patent_doc_number] => 20210064811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION [patent_app_type] => utility [patent_app_number] => 17/097106 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18053259 [patent_doc_number] => 11526644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Controlling test networks of chips using integrated processors [patent_app_type] => utility [patent_app_number] => 17/089864 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17499722 [patent_doc_number] => 11288428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Integrated circuit design modification for localization of scan chain defects [patent_app_type] => utility [patent_app_number] => 17/085830 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18471676 [patent_doc_number] => 20230205962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => AUTOMATIC LAYOUT METHOD FOR PAD RING USED FOR OPTIMIZING ELECTROSTATIC DISCHARGING CAPACITY OF CHIP [patent_app_type] => utility [patent_app_number] => 17/595632 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 732 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17409310 [patent_doc_number] => 11250197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Channel less floor-planning in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/079727 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7245 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17564902 [patent_doc_number] => 20220129051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => PASSIVELY COOLING HARDWARE COMPONENTS [patent_app_type] => utility [patent_app_number] => 17/077361 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17550456 [patent_doc_number] => 20220121798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Circuit Synthesis Optimization for Implements on Integrated Circuit [patent_app_type] => utility [patent_app_number] => 17/075760 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17528916 [patent_doc_number] => 11301605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => System and method of prototyping virtual circuits with physical proxies [patent_app_type] => utility [patent_app_number] => 17/072763 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072763 [rel_patent_id] =>[rel_patent_doc_number] =>)