Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16130563 [patent_doc_number] => 10699043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Generating integrated circuit floorplans using neural networks [patent_app_type] => utility [patent_app_number] => 16/703837 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7458 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703837
Generating integrated circuit floorplans using neural networks Dec 3, 2019 Issued
Array ( [id] => 18720402 [patent_doc_number] => 11797748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Method for generating patterning device pattern at patch boundary [patent_app_type] => utility [patent_app_number] => 17/418102 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 15904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17418102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/418102
Method for generating patterning device pattern at patch boundary Nov 17, 2019 Issued
Array ( [id] => 17335428 [patent_doc_number] => 20220001759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => UNDERFLOOR CHARGING UNIT AND VEHICLE HAVING AN UNDERFLOOR CHARGING UNIT [patent_app_type] => utility [patent_app_number] => 17/294227 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17294227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/294227
UNDERFLOOR CHARGING UNIT AND VEHICLE HAVING AN UNDERFLOOR CHARGING UNIT Nov 14, 2019 Abandoned
Array ( [id] => 17106562 [patent_doc_number] => 11126780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Automatic net grouping and routing [patent_app_type] => utility [patent_app_number] => 16/680210 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 9149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680210
Automatic net grouping and routing Nov 10, 2019 Issued
Array ( [id] => 16895356 [patent_doc_number] => 11036912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Overlay optimization [patent_app_type] => utility [patent_app_number] => 16/679826 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679826
Overlay optimization Nov 10, 2019 Issued
Array ( [id] => 19536233 [patent_doc_number] => 12128772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Semiconductor unit, battery unit, and vehicle [patent_app_type] => utility [patent_app_number] => 17/288825 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 60 [patent_no_of_words] => 27190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17288825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/288825
Semiconductor unit, battery unit, and vehicle Oct 29, 2019 Issued
Array ( [id] => 17415477 [patent_doc_number] => 20220050381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => METHOD FOR DETERMINING PATTERNING DEVICE PATTERN BASED ON MANUFACTURABILITY [patent_app_type] => utility [patent_app_number] => 17/297801 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17297801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/297801
Method for determining patterning device pattern based on manufacturability Oct 28, 2019 Issued
Array ( [id] => 15843115 [patent_doc_number] => 20200136840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => PUF CELL ARRAY, SYSTEM AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/661971 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661971
PUF cell array, system and method of manufacturing same Oct 22, 2019 Issued
Array ( [id] => 17276195 [patent_doc_number] => 20210382393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => FAILURE MODEL FOR PREDICTING FAILURE DUE TO RESIST LAYER [patent_app_type] => utility [patent_app_number] => 17/288167 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17288167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/288167
Failure model for predicting failure due to resist layer Oct 21, 2019 Issued
Array ( [id] => 17033325 [patent_doc_number] => 11095148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Series-connected battery packs, system and method [patent_app_type] => utility [patent_app_number] => 16/654203 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654203
Series-connected battery packs, system and method Oct 15, 2019 Issued
Array ( [id] => 17254361 [patent_doc_number] => 11189864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Electronic device and control method [patent_app_type] => utility [patent_app_number] => 16/592922 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6907 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592922
Electronic device and control method Oct 3, 2019 Issued
Array ( [id] => 16001907 [patent_doc_number] => 20200176824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => MOLTEN SALT BATTERY WITH SOLID METAL CATHODE [patent_app_type] => utility [patent_app_number] => 16/593278 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593278
Molten salt battery with solid metal cathode Oct 3, 2019 Issued
Array ( [id] => 19090432 [patent_doc_number] => 11951858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Charging device for connecting an electrical energy store of a motor vehicle to a charging station [patent_app_type] => utility [patent_app_number] => 17/288066 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4562 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17288066 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/288066
Charging device for connecting an electrical energy store of a motor vehicle to a charging station Sep 29, 2019 Issued
Array ( [id] => 16818991 [patent_doc_number] => 11003825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => System, method, and computer program product for optimization in an electronic design [patent_app_type] => utility [patent_app_number] => 16/583643 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583643
System, method, and computer program product for optimization in an electronic design Sep 25, 2019 Issued
Array ( [id] => 15713995 [patent_doc_number] => 20200103764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => LITHOGRAPHY SIMULATION METHOD [patent_app_type] => utility [patent_app_number] => 16/584396 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584396
Lithography simulation method Sep 25, 2019 Issued
Array ( [id] => 16802385 [patent_doc_number] => 10997332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => System and method for computing electrical over-stress of devices associated with an electronic design [patent_app_type] => utility [patent_app_number] => 16/583803 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583803
System and method for computing electrical over-stress of devices associated with an electronic design Sep 25, 2019 Issued
Array ( [id] => 16675952 [patent_doc_number] => 20210064718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/559874 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559874 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559874
Superconducting circuit with virtual timing elements and related methods Sep 3, 2019 Issued
Array ( [id] => 17062245 [patent_doc_number] => 11106850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Flexible constraint-based logic cell placement [patent_app_type] => utility [patent_app_number] => 16/559976 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559976
Flexible constraint-based logic cell placement Sep 3, 2019 Issued
Array ( [id] => 16943221 [patent_doc_number] => 11055465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Fill techniques for avoiding Boolean DRC failures during cell placement [patent_app_type] => utility [patent_app_number] => 16/559967 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559967
Fill techniques for avoiding Boolean DRC failures during cell placement Sep 3, 2019 Issued
Array ( [id] => 16788311 [patent_doc_number] => 10990745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Integrated circuit and method of forming same and a system [patent_app_type] => utility [patent_app_number] => 16/559534 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 14181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559534
Integrated circuit and method of forming same and a system Sep 2, 2019 Issued
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