Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18493599 [patent_doc_number] => 11699017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Die yield assessment based on pattern-failure rate simulation [patent_app_type] => utility [patent_app_number] => 17/417223 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/417223
Die yield assessment based on pattern-failure rate simulation Aug 22, 2019 Issued
Array ( [id] => 17017423 [patent_doc_number] => 11087065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Method of manufacturing devices [patent_app_type] => utility [patent_app_number] => 16/541420 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9973 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541420 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541420
Method of manufacturing devices Aug 14, 2019 Issued
Array ( [id] => 15871391 [patent_doc_number] => 20200143099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => WAFER-TO-DESIGN IMAGE ANALYSIS (WDIA) SYSTEM [patent_app_type] => utility [patent_app_number] => 16/542087 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542087
Wafer-to-design image analysis (WDIA) system Aug 14, 2019 Issued
Array ( [id] => 16526673 [patent_doc_number] => 20200400753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => CHARGING LOAD DETECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/536832 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536832 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536832
Charging load detection circuit Aug 8, 2019 Issued
Array ( [id] => 19228795 [patent_doc_number] => 12008433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Variational quantum state preparation [patent_app_type] => utility [patent_app_number] => 16/967339 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5478 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16967339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/967339
Variational quantum state preparation Aug 6, 2019 Issued
Array ( [id] => 15091039 [patent_doc_number] => 20190340330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Method for Integrated Circuit Manufacturing [patent_app_type] => utility [patent_app_number] => 16/516853 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516853
Method for integrated circuit manufacturing Jul 18, 2019 Issued
Array ( [id] => 16385509 [patent_doc_number] => 10810348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Constructing colorable wiring layouts with wide wires and sandwich rules [patent_app_type] => utility [patent_app_number] => 16/511884 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511884
Constructing colorable wiring layouts with wide wires and sandwich rules Jul 14, 2019 Issued
Array ( [id] => 17106554 [patent_doc_number] => 11126772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Tools and methods for designing a circuit, and circuits made thereby [patent_app_type] => utility [patent_app_number] => 16/511541 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 11675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511541
Tools and methods for designing a circuit, and circuits made thereby Jul 14, 2019 Issued
Array ( [id] => 16535553 [patent_doc_number] => 10878154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Evaluation of nets for suitability of time domain multiplexing during partitioning and placing a circuit design [patent_app_type] => utility [patent_app_number] => 16/510600 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4477 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510600 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510600
Evaluation of nets for suitability of time domain multiplexing during partitioning and placing a circuit design Jul 11, 2019 Issued
Array ( [id] => 17056416 [patent_doc_number] => 20210265850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => MANAGEMENT SERVER, MANAGEMENT SYSTEM, AND MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/256174 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17256174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/256174
Management server, management system, and management method Jun 12, 2019 Issued
Array ( [id] => 16355557 [patent_doc_number] => 10796069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Bump connection placement in quantum devices in a flip chip configuration [patent_app_type] => utility [patent_app_number] => 16/433253 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/433253
Bump connection placement in quantum devices in a flip chip configuration Jun 5, 2019 Issued
Array ( [id] => 16338444 [patent_doc_number] => 10789404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-29 [patent_title] => System, method, and computer program product for generating a formal verification model [patent_app_type] => utility [patent_app_number] => 16/434129 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/434129
System, method, and computer program product for generating a formal verification model Jun 5, 2019 Issued
Array ( [id] => 16431885 [patent_doc_number] => 10831971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Net layer promotion with swap capability in electronic design [patent_app_type] => utility [patent_app_number] => 16/431974 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431974 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431974
Net layer promotion with swap capability in electronic design Jun 4, 2019 Issued
Array ( [id] => 16463108 [patent_doc_number] => 10846457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Lithography system, simulation apparatus, and pattern forming method [patent_app_type] => utility [patent_app_number] => 16/431221 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 17118 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431221
Lithography system, simulation apparatus, and pattern forming method Jun 3, 2019 Issued
Array ( [id] => 18890922 [patent_doc_number] => 11869699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Inductive energy emitter/receiver for an inductive charger of an electric vehicle [patent_app_type] => utility [patent_app_number] => 17/057335 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17057335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/057335
Inductive energy emitter/receiver for an inductive charger of an electric vehicle May 20, 2019 Issued
Array ( [id] => 16921171 [patent_doc_number] => 20210194263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => ENERGY STORAGE APPARATUS, EXTERNAL DISCHARGE DEVICE, AND DISCHARGE METHOD OF ENERGY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/056996 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17056996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/056996
Energy storage apparatus, external discharge device, and discharge method of energy storage device May 15, 2019 Issued
Array ( [id] => 14751199 [patent_doc_number] => 20190258773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => Method and System for Determining Circuit Failure Rate [patent_app_type] => utility [patent_app_number] => 16/404678 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404678
Method and system for determining circuit failure rate May 5, 2019 Issued
Array ( [id] => 17757547 [patent_doc_number] => 11397840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Edge placement errors for optical lithography [patent_app_type] => utility [patent_app_number] => 16/353888 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8106 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353888
Edge placement errors for optical lithography Mar 13, 2019 Issued
Array ( [id] => 17365226 [patent_doc_number] => 11232249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Method for determining curvilinear patterns for patterning device [patent_app_type] => utility [patent_app_number] => 16/976492 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 13871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/976492
Method for determining curvilinear patterns for patterning device Feb 27, 2019 Issued
Array ( [id] => 17223798 [patent_doc_number] => 11176300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Systems and methods for creating individualized processing chips and assemblies [patent_app_type] => utility [patent_app_number] => 16/266043 [patent_app_country] => US [patent_app_date] => 2019-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 23052 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/266043
Systems and methods for creating individualized processing chips and assemblies Feb 1, 2019 Issued
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