Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16447202 [patent_doc_number] => 10839131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Three-dimensional mask model for photolithography simulation [patent_app_type] => utility [patent_app_number] => 16/265367 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12953 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/265367
Three-dimensional mask model for photolithography simulation Jan 31, 2019 Issued
Array ( [id] => 19327867 [patent_doc_number] => 12045555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Method to label substrates based on process parameters [patent_app_type] => utility [patent_app_number] => 16/960376 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 14563 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16960376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/960376
Method to label substrates based on process parameters Jan 21, 2019 Issued
Array ( [id] => 16987215 [patent_doc_number] => 11074391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips [patent_app_type] => utility [patent_app_number] => 16/253812 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10515 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253812
Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips Jan 21, 2019 Issued
Array ( [id] => 14873061 [patent_doc_number] => 20190286772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => Adjustable Integrated Circuits and Methods for Designing the Same [patent_app_type] => utility [patent_app_number] => 16/250424 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250424
Adjustable integrated circuits and methods for designing the same Jan 16, 2019 Issued
Array ( [id] => 15653199 [patent_doc_number] => 20200089130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Optical Mode Optimization for Wafer Inspection [patent_app_type] => utility [patent_app_number] => 16/250128 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250128
Optical mode optimization for wafer inspection Jan 16, 2019 Issued
Array ( [id] => 18031030 [patent_doc_number] => 11514220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Predicting power usage of a chip [patent_app_type] => utility [patent_app_number] => 16/243362 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243362
Predicting power usage of a chip Jan 8, 2019 Issued
Array ( [id] => 16171835 [patent_doc_number] => 10713407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Standard cell and semiconductor device including anchor nodes [patent_app_type] => utility [patent_app_number] => 16/231840 [patent_app_country] => US [patent_app_date] => 2018-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231840
Standard cell and semiconductor device including anchor nodes Dec 23, 2018 Issued
Array ( [id] => 14788239 [patent_doc_number] => 20190269017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => APPARATUS AND METHOD OF GENERATING CONTROL PARAMETER OF SCREEN PRINTER [patent_app_type] => utility [patent_app_number] => 16/229421 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229421
Apparatus and method of generating control parameter of screen printer Dec 20, 2018 Issued
Array ( [id] => 17062244 [patent_doc_number] => 11106849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Method for generating redundant configuration in FPGAs [patent_app_type] => utility [patent_app_number] => 16/348810 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6240 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16348810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/348810
Method for generating redundant configuration in FPGAs Dec 19, 2018 Issued
Array ( [id] => 15658437 [patent_doc_number] => 20200091749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => PORTABLE POWER SOURCE [patent_app_type] => utility [patent_app_number] => 16/226659 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226659
PORTABLE POWER SOURCE Dec 19, 2018 Abandoned
Array ( [id] => 16146261 [patent_doc_number] => 10706202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Devices and methods for balanced routing tree structures [patent_app_type] => utility [patent_app_number] => 16/228473 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228473
Devices and methods for balanced routing tree structures Dec 19, 2018 Issued
Array ( [id] => 16292493 [patent_doc_number] => 10769345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-08 [patent_title] => Clock tree optimization by moving instances toward core route [patent_app_type] => utility [patent_app_number] => 16/228451 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228451
Clock tree optimization by moving instances toward core route Dec 19, 2018 Issued
Array ( [id] => 16575213 [patent_doc_number] => 10897143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Passive cell-balancing with dynamic charge control [patent_app_type] => utility [patent_app_number] => 16/228338 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228338
Passive cell-balancing with dynamic charge control Dec 19, 2018 Issued
Array ( [id] => 15855463 [patent_doc_number] => 10643019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => View pruning for routing tree optimization [patent_app_type] => utility [patent_app_number] => 16/228494 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228494 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228494
View pruning for routing tree optimization Dec 19, 2018 Issued
Array ( [id] => 14510931 [patent_doc_number] => 20190199120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => CHARGING STATION MOUNTED ON A POWERED DRIVEABLE MACHINE [patent_app_type] => utility [patent_app_number] => 16/226833 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226833
Charging station mounted on a powered driveable machine Dec 19, 2018 Issued
Array ( [id] => 16355537 [patent_doc_number] => 10796049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Waveform propagation timing modeling for circuit design [patent_app_type] => utility [patent_app_number] => 16/228481 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228481
Waveform propagation timing modeling for circuit design Dec 19, 2018 Issued
Array ( [id] => 16232980 [patent_doc_number] => 10740532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Route driven placement of fan-out clock drivers [patent_app_type] => utility [patent_app_number] => 16/228432 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228432
Route driven placement of fan-out clock drivers Dec 19, 2018 Issued
Array ( [id] => 16232978 [patent_doc_number] => 10740530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-11 [patent_title] => Clock tree wirelength reduction based on a target offset in connected routes [patent_app_type] => utility [patent_app_number] => 16/228439 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228439
Clock tree wirelength reduction based on a target offset in connected routes Dec 19, 2018 Issued
Array ( [id] => 14510581 [patent_doc_number] => 20190198945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SECONDARY BATTERY SYSTEM AND METHOD FOR DIAGNOSING ABNORMALITY IN BATTERY PACK [patent_app_type] => utility [patent_app_number] => 16/227768 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227768 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227768
Secondary battery system and method for diagnosing abnormality in battery pack Dec 19, 2018 Issued
Array ( [id] => 15333295 [patent_doc_number] => 20200006977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => ELECTRONIC DEVICE AND CHARGING CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/207523 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207523
Electronic device and charging control method Dec 2, 2018 Issued
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