Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19552219 [patent_doc_number] => 12135928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Constraints and objectives used in synthesis of a network-on-chip (NoC) [patent_app_type] => utility [patent_app_number] => 18/530164 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 7959 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530164
Constraints and objectives used in synthesis of a network-on-chip (NoC) Dec 4, 2023 Issued
Array ( [id] => 19036795 [patent_doc_number] => 20240086610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => BLOCK LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS [patent_app_type] => utility [patent_app_number] => 18/513349 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513349
Block level design method for heterogeneous PG-structure cells Nov 16, 2023 Issued
Array ( [id] => 20001125 [patent_doc_number] => 20250139347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => COUPON AND METHOD FOR INTERNAL REGISTRATION FOR MAXIMIZING BACKDRILL-TO-METAL CLEARANCE [patent_app_type] => utility [patent_app_number] => 18/497203 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/497203
COUPON AND METHOD FOR INTERNAL REGISTRATION FOR MAXIMIZING BACKDRILL-TO-METAL CLEARANCE Oct 29, 2023 Pending
Array ( [id] => 19053468 [patent_doc_number] => 20240095437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => METHOD FOR GENERATING PATTERNING DEVICE PATTERN AT PATCH BOUNDARY [patent_app_type] => utility [patent_app_number] => 18/382822 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18382822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/382822
Method for generating patterning device pattern at patch boundary Oct 22, 2023 Issued
Array ( [id] => 19992950 [patent_doc_number] => 20250131172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Negative Group Delay Filters based on Reciprocal-capped Butterworth, and Reciprocal-capped Chebyshev low-pass filter transfer functions [patent_app_type] => utility [patent_app_number] => 18/491922 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491922
Negative Group Delay Filters based on Reciprocal-capped Butterworth, and Reciprocal-capped Chebyshev low-pass filter transfer functions Oct 22, 2023 Pending
Array ( [id] => 19992953 [patent_doc_number] => 20250131175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => Systems and Methods for Floating Point to Quantized Grid Sampling [patent_app_type] => utility [patent_app_number] => 18/491611 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491611
Systems and methods for floating point to quantized grid sampling Oct 19, 2023 Issued
Array ( [id] => 19985977 [patent_doc_number] => 20250124199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => Arithmetic Circuit Design and Evaluation Using Backward Error Analysis [patent_app_type] => utility [patent_app_number] => 18/379962 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379962 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379962
Arithmetic Circuit Design and Evaluation Using Backward Error Analysis Oct 12, 2023 Pending
Array ( [id] => 18897493 [patent_doc_number] => 20240012978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => USE OF ADAPTIVE REPLACEMENT MAPS IN DIGITAL LITHOGRAPHY FOR LOCAL CELL REPLACEMENT [patent_app_type] => utility [patent_app_number] => 18/470717 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470717
Use of adaptive replacement maps in digital lithography for local cell replacement Sep 19, 2023 Issued
Array ( [id] => 18957695 [patent_doc_number] => 20240046022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHODS FOR SAMPLE SCHEME GENERATION AND OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/239814 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239814
Methods for sample scheme generation and optimization Aug 29, 2023 Issued
Array ( [id] => 19085135 [patent_doc_number] => 20240111936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => ROUTING METHOD FOR CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/235911 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235911
ROUTING METHOD FOR CIRCUIT BOARD Aug 20, 2023 Pending
Array ( [id] => 18847394 [patent_doc_number] => 20230409798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD OF MAKING CELL REGIONS OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/448115 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448115
Method of making cell regions of integrated circuits Aug 9, 2023 Issued
Array ( [id] => 19639063 [patent_doc_number] => 12169671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Apparatus and method for mapping foundational components during design porting from one process technology to another process technology [patent_app_type] => utility [patent_app_number] => 18/231762 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231762
Apparatus and method for mapping foundational components during design porting from one process technology to another process technology Aug 7, 2023 Issued
Array ( [id] => 19872913 [patent_doc_number] => 12265775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Semiconductor device with reduced power [patent_app_type] => utility [patent_app_number] => 18/362810 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 23949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362810
Semiconductor device with reduced power Jul 30, 2023 Issued
Array ( [id] => 19639068 [patent_doc_number] => 12169676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => PUF cell array, system and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 18/362912 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 47 [patent_no_of_words] => 29672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362912
PUF cell array, system and method of manufacturing same Jul 30, 2023 Issued
Array ( [id] => 20131311 [patent_doc_number] => 12373624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Systems and methods for multi-bit memory with embedded logic [patent_app_type] => utility [patent_app_number] => 18/359069 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 1142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359069
Systems and methods for multi-bit memory with embedded logic Jul 25, 2023 Issued
Array ( [id] => 19719303 [patent_doc_number] => 12204842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Optical mode optimization for wafer inspection [patent_app_type] => utility [patent_app_number] => 18/359648 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359648
Optical mode optimization for wafer inspection Jul 25, 2023 Issued
Array ( [id] => 19159971 [patent_doc_number] => 20240152678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => ELEMENT SEARCH METHOD AND APPARATUS, COMPUTER DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/226672 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226672
ELEMENT SEARCH METHOD AND APPARATUS, COMPUTER DEVICE AND STORAGE MEDIUM Jul 25, 2023 Pending
Array ( [id] => 19443354 [patent_doc_number] => 12093623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Relocatable FPGA modules [patent_app_type] => utility [patent_app_number] => 18/226108 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226108
Relocatable FPGA modules Jul 24, 2023 Issued
Array ( [id] => 18957686 [patent_doc_number] => 20240046013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => CHIP PLACEMENT METHOD AND APPARATUS, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/355754 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355754
CHIP PLACEMENT METHOD AND APPARATUS, AND STORAGE MEDIUM Jul 19, 2023 Pending
Array ( [id] => 19764960 [patent_doc_number] => 12223251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Standard cell and semiconductor device including anchor nodes [patent_app_type] => utility [patent_app_number] => 18/355283 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355283
Standard cell and semiconductor device including anchor nodes Jul 18, 2023 Issued
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