Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10550551 [patent_doc_number] => 09275177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Semi-local ballistic mobility model' [patent_app_type] => utility [patent_app_number] => 14/283082 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 15736 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14283082 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/283082
Semi-local ballistic mobility model May 19, 2014 Issued
Array ( [id] => 10446976 [patent_doc_number] => 20150331990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT FORMATION' [patent_app_type] => utility [patent_app_number] => 14/279462 [patent_app_country] => US [patent_app_date] => 2014-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279462
Semiconductor arrangement formation May 15, 2014 Issued
Array ( [id] => 10589824 [patent_doc_number] => 09311442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Net-voltage-aware optical proximity correction (OPC)' [patent_app_type] => utility [patent_app_number] => 14/261632 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5848 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261632
Net-voltage-aware optical proximity correction (OPC) Apr 24, 2014 Issued
Array ( [id] => 10418134 [patent_doc_number] => 20150303145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/255820 [patent_app_country] => US [patent_app_date] => 2014-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4846 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14255820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/255820
BACK END OF LINE (BEOL) LOCAL OPTIMIZATION TO IMPROVE PRODUCT PERFORMANCE Apr 16, 2014 Abandoned
Array ( [id] => 10904489 [patent_doc_number] => 20140307501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS' [patent_app_type] => utility [patent_app_number] => 14/250370 [patent_app_country] => US [patent_app_date] => 2014-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14250370 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/250370
Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers Apr 9, 2014 Issued
Array ( [id] => 9787852 [patent_doc_number] => 20140304672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'Hierarchical Testing Architecture Using Core Circuit with Pseudo-Interfaces' [patent_app_type] => utility [patent_app_number] => 14/243602 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8158 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243602 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243602
Hierarchical testing architecture using core circuit with pseudo-interfaces Apr 1, 2014 Issued
Array ( [id] => 10401754 [patent_doc_number] => 20150286763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'PATTERN MATCHING FOR PREDICTING DEFECT LIMITED YIELD' [patent_app_type] => utility [patent_app_number] => 14/243551 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243551
PATTERN MATCHING FOR PREDICTING DEFECT LIMITED YIELD Apr 1, 2014 Abandoned
Array ( [id] => 10395435 [patent_doc_number] => 20150280442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'TESSELLATED INDUCTIVE POWER TRANSMISSION SYSTEM COIL CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/225067 [patent_app_country] => US [patent_app_date] => 2014-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5837 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/225067
Tessellated inductive power transmission system coil configurations Mar 24, 2014 Issued
Array ( [id] => 10610181 [patent_doc_number] => 09330215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Method and system for verifying the design of an integrated circuit having multiple tiers' [patent_app_type] => utility [patent_app_number] => 14/219029 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219029
Method and system for verifying the design of an integrated circuit having multiple tiers Mar 18, 2014 Issued
Array ( [id] => 10610181 [patent_doc_number] => 09330215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Method and system for verifying the design of an integrated circuit having multiple tiers' [patent_app_type] => utility [patent_app_number] => 14/219029 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219029 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219029
Method and system for verifying the design of an integrated circuit having multiple tiers Mar 18, 2014 Issued
Array ( [id] => 10384295 [patent_doc_number] => 20150269302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'ELECTROMIGRATION-AWARE LAYOUT GENERATION' [patent_app_type] => utility [patent_app_number] => 14/218147 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218147
Electromigration-aware layout generation Mar 17, 2014 Issued
Array ( [id] => 9746596 [patent_doc_number] => 20140282315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'GRAPHICAL VIEW AND DEBUG FOR COVERAGE-POINT NEGATIVE HINT' [patent_app_type] => utility [patent_app_number] => 14/208142 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14208142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/208142
Graphical view and debug for coverage-point negative hint Mar 12, 2014 Issued
Array ( [id] => 11764525 [patent_doc_number] => 09372952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques' [patent_app_type] => utility [patent_app_number] => 14/201772 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12474 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14201772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/201772
Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques Mar 6, 2014 Issued
Array ( [id] => 10368368 [patent_doc_number] => 20150253373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'DYNAMIC YIELD PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/196219 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/196219
Dynamic yield prediction Mar 3, 2014 Issued
Array ( [id] => 11578719 [patent_doc_number] => 09633987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Integrated circuit cell library for multiple patterning' [patent_app_type] => utility [patent_app_number] => 14/195600 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 9527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14195600 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/195600
Integrated circuit cell library for multiple patterning Mar 2, 2014 Issued
Array ( [id] => 10362885 [patent_doc_number] => 20150247890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-03 [patent_title] => 'CALCULATING CIRCUIT-LEVEL LEAKAGE USING THREE DIMENSIONAL TECHNOLOGY COMPUTER AIDED DESIGN AND A REDUCED NUMBER OF TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/194225 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/194225
Calculating circuit-level leakage using three dimensional technology computer aided design and a reduced number of transistors Feb 27, 2014 Issued
Array ( [id] => 10577495 [patent_doc_number] => 09300151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Wireless charging device' [patent_app_type] => utility [patent_app_number] => 14/188770 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5268 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188770
Wireless charging device Feb 24, 2014 Issued
Array ( [id] => 10223957 [patent_doc_number] => 20150108950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'BATTERY PACK, ENERGY STORAGE SYSTEM INCLUDING BATTERY PACK, AND METHOD OF CHARGING BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 14/188627 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10957 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188627
Battery pack, energy storage system including battery pack, and method of charging battery pack Feb 23, 2014 Issued
Array ( [id] => 9683142 [patent_doc_number] => 20140239905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'ELECTROCHEMICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 14/187562 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187562
ELECTROCHEMICAL DEVICE Feb 23, 2014 Abandoned
Array ( [id] => 9683127 [patent_doc_number] => 20140239890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Hands free conductive charging system for Electric Vehicles' [patent_app_type] => utility [patent_app_number] => 14/187321 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1563 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187321 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187321
Hands free conductive charging system for electric vehicles Feb 23, 2014 Issued
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