Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9954534 [patent_doc_number] => 09003348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Placing transistors in proximity to through-silicon vias' [patent_app_type] => utility [patent_app_number] => 14/188532 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11624 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188532
Placing transistors in proximity to through-silicon vias Feb 23, 2014 Issued
Array ( [id] => 11709251 [patent_doc_number] => 20170177750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Majority Logic Synthesis' [patent_app_type] => utility [patent_app_number] => 15/118490 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6978 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15118490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/118490
Majority logic synthesis Feb 19, 2014 Issued
Array ( [id] => 9540371 [patent_doc_number] => 20140165018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'SEMICONDUCTOR DEVICE, ADJUSTMENT METHOD THEREOF AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/179365 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17903 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179365
Semiconductor device, adjustment method thereof and data processing system Feb 11, 2014 Issued
Array ( [id] => 10320895 [patent_doc_number] => 20150205899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'IMPLEMENTING ENHANCED PHYSICAL DESIGN QUALITY USING HISTORICAL PLACEMENT ANALYTICS' [patent_app_type] => utility [patent_app_number] => 14/162304 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3511 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162304
Implementing enhanced physical design quality using historical placement analytics Jan 22, 2014 Issued
Array ( [id] => 10301583 [patent_doc_number] => 20150186584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'UNIT FILL FOR INTEGRATED CIRCUIT DESIGN FOR MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 14/156877 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5182 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156877 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156877
Unit fill for integrated circuit design for manufacturing Jan 15, 2014 Issued
Array ( [id] => 9829456 [patent_doc_number] => 08938695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-20 [patent_title] => 'Signature analytics for improving lithographic process of manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/150772 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2359 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/150772
Signature analytics for improving lithographic process of manufacturing semiconductor devices Jan 8, 2014 Issued
Array ( [id] => 10841392 [patent_doc_number] => 08869092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Wiring inspection apparatus and wiring inspection method' [patent_app_type] => utility [patent_app_number] => 14/146752 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10860 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146752
Wiring inspection apparatus and wiring inspection method Jan 2, 2014 Issued
Array ( [id] => 10307513 [patent_doc_number] => 20150192514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'Scatterometry Metrology Methods And Methods Of Modeling Formation Of A Vertical Region Of A Multilayer Semiconductor Substrate To Comprise A Scatterometry Target' [patent_app_type] => utility [patent_app_number] => 14/147417 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4374 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147417
Scatterometry metrology methods and methods of modeling formation of a vertical region of a multilayer semiconductor substrate to comprise a scatterometry target Jan 2, 2014 Issued
Array ( [id] => 11830943 [patent_doc_number] => 09727686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Method for finding non-essential flip flops in a VLSI design that do not require retention in standby mode' [patent_app_type] => utility [patent_app_number] => 14/758927 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11977 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14758927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/758927
Method for finding non-essential flip flops in a VLSI design that do not require retention in standby mode Jan 1, 2014 Issued
Array ( [id] => 10301580 [patent_doc_number] => 20150186580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SYSTEM AND METHOD FOR AMPLIFIER DESIGN' [patent_app_type] => utility [patent_app_number] => 14/144695 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8027 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144695
System and method for amplifier design Dec 30, 2013 Issued
Array ( [id] => 9437647 [patent_doc_number] => 20140115554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE' [patent_app_type] => utility [patent_app_number] => 14/145157 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9643 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145157 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145157
METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE Dec 30, 2013 Abandoned
Array ( [id] => 10301584 [patent_doc_number] => 20150186583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SYSTEM FOR AND METHOD OF TUNING CLOCK NETWORKS CONSTRUCTED USING VARIABLE DRIVE-STRENGTH CLOCK INVERTERS WITH VARIABLE DRIVE-STRENGTH CLOCK DRIVERS BUILT OUT OF A SMALLER SUBSET OF BASE CELLS' [patent_app_type] => utility [patent_app_number] => 14/141104 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7639 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14141104 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/141104
System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells Dec 25, 2013 Issued
Array ( [id] => 10002489 [patent_doc_number] => 09046573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-02 [patent_title] => 'Addressable test arrays for characterizing integrated circuit device parameters' [patent_app_type] => utility [patent_app_number] => 14/137772 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7337 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137772
Addressable test arrays for characterizing integrated circuit device parameters Dec 19, 2013 Issued
Array ( [id] => 10284820 [patent_doc_number] => 20150169818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'PATTERN-BASED VIA REDUNDANCY INSERTION' [patent_app_type] => utility [patent_app_number] => 14/132926 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132926 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132926
Pattern-based via redundancy insertion Dec 17, 2013 Issued
Array ( [id] => 9758989 [patent_doc_number] => 20140289689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'WIRING INSPECTION APPARATUS AND WIRING INSPECTION METHOD' [patent_app_type] => utility [patent_app_number] => 14/132542 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9170 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132542 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132542
Wiring inspection apparatus and wiring inspection method Dec 17, 2013 Issued
Array ( [id] => 9847820 [patent_doc_number] => 08949754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-03 [patent_title] => 'System, method, and computer program product for verification using X-propagation' [patent_app_type] => utility [patent_app_number] => 14/108902 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/108902
System, method, and computer program product for verification using X-propagation Dec 16, 2013 Issued
Array ( [id] => 9940921 [patent_doc_number] => 08990752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Method for automatic design of an electronic circuit, corresponding system, and computer program product' [patent_app_type] => utility [patent_app_number] => 14/108462 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7750 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/108462
Method for automatic design of an electronic circuit, corresponding system, and computer program product Dec 16, 2013 Issued
Array ( [id] => 10276323 [patent_doc_number] => 20150161320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/100673 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100673 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100673
SCATTERING BAR OPTIMIZATION APPARATUS AND METHOD Dec 8, 2013 Abandoned
Array ( [id] => 9540370 [patent_doc_number] => 20140165017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/100712 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12766 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100712
Physics-based reliability model for large-scale CMOS circuit design Dec 8, 2013 Issued
Array ( [id] => 10131264 [patent_doc_number] => 09165100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Methods and apparatus to map schematic elements into a database' [patent_app_type] => utility [patent_app_number] => 14/097432 [patent_app_country] => US [patent_app_date] => 2013-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5046 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097432 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/097432
Methods and apparatus to map schematic elements into a database Dec 4, 2013 Issued
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