Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19419480 [patent_doc_number] => 20240295603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/350512 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350512
DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME Jul 10, 2023 Pending
Array ( [id] => 18942170 [patent_doc_number] => 20240037309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => MULTIPLEXER [patent_app_type] => utility [patent_app_number] => 18/345389 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345389
Multiplexer Jun 29, 2023 Issued
Array ( [id] => 19685839 [patent_doc_number] => 20250004384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => METROLOGY IN THE PRESENCE OF CMOS UNDER ARRAY (CUA) STRUCTURES UTILIZING AN EFFECTIVE MEDIUM MODEL WITH CLASSIFICATION OF CUA STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/217199 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217199
Metrology in the presence of CMOS under array (CUA) structures utilizing an effective medium model with classification of CUA structures Jun 29, 2023 Issued
Array ( [id] => 19686704 [patent_doc_number] => 20250005249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY [patent_app_type] => utility [patent_app_number] => 18/344766 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344766
SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY Jun 28, 2023 Pending
Array ( [id] => 18864714 [patent_doc_number] => 20230419151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => METHODS AND APPARATUSES FOR MULTIPURPOSE LIGHT COLLECTION FOR REMOTELY ENTANGLING ATOMIC QUANTUM COMPUTERS IN A MULTI-CORE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/339786 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339786
METHODS AND APPARATUSES FOR MULTIPURPOSE LIGHT COLLECTION FOR REMOTELY ENTANGLING ATOMIC QUANTUM COMPUTERS IN A MULTI-CORE ARCHITECTURE Jun 21, 2023 Pending
Array ( [id] => 18711590 [patent_doc_number] => 20230334219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING SAME AND A SYSTEM [patent_app_type] => utility [patent_app_number] => 18/337245 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337245
Integrated circuit and method of forming same and a system Jun 18, 2023 Issued
Array ( [id] => 19645482 [patent_doc_number] => 20240420002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => IMPLEMENTING NET COHERENT ROTATIONS DURING DYNAMICAL DECOUPLING [patent_app_type] => utility [patent_app_number] => 18/336656 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336656
IMPLEMENTING NET COHERENT ROTATIONS DURING DYNAMICAL DECOUPLING Jun 15, 2023 Pending
Array ( [id] => 19530581 [patent_doc_number] => 20240354483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => BUFFER COMPATIBLE WITH SKEW CRITICAL PROTOCOLS IMPLEMENTED IN AN INTEGRATED CIRCUIT AND METHODS FOR ROUTING METAL LINES TO THE BUFFER IN THE INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/335184 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335184
BUFFER COMPATIBLE WITH SKEW CRITICAL PROTOCOLS IMPLEMENTED IN AN INTEGRATED CIRCUIT AND METHODS FOR ROUTING METAL LINES TO THE BUFFER IN THE INTEGRATED CIRCUIT Jun 14, 2023 Pending
Array ( [id] => 19259915 [patent_doc_number] => 12019974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Geometric mask rule check with favorable and unfavorable zones [patent_app_type] => utility [patent_app_number] => 18/334551 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334551
Geometric mask rule check with favorable and unfavorable zones Jun 13, 2023 Issued
Array ( [id] => 18998095 [patent_doc_number] => 11914942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Method for predicting resist deformation [patent_app_type] => utility [patent_app_number] => 18/206029 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 28919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206029
Method for predicting resist deformation Jun 4, 2023 Issued
Array ( [id] => 19603672 [patent_doc_number] => 20240394552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Routability-Aware Large-Scale Transistor-Level Placement Using Reinforcement Learning [patent_app_type] => utility [patent_app_number] => 18/202029 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202029
Routability-Aware Large-Scale Transistor-Level Placement Using Reinforcement Learning May 24, 2023 Pending
Array ( [id] => 18813479 [patent_doc_number] => 20230387816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FABRICATION TRADE-OFF BASED OPTIMAL SYNTHESIS OF WINDING CONFIGURATIONS FOR PLANAR TRANSFORMER IN CAPACITOR-INDUCTOR-INDUCTOR-CAPACITOR (CLLC) DIRECT CURRENT (DC)-DC CONVERTER [patent_app_type] => utility [patent_app_number] => 18/323980 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323980
FABRICATION TRADE-OFF BASED OPTIMAL SYNTHESIS OF WINDING CONFIGURATIONS FOR PLANAR TRANSFORMER IN CAPACITOR-INDUCTOR-INDUCTOR-CAPACITOR (CLLC) DIRECT CURRENT (DC)-DC CONVERTER May 24, 2023 Pending
Array ( [id] => 19198148 [patent_doc_number] => 11995386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Verification of hardware design for data transformation component [patent_app_type] => utility [patent_app_number] => 18/201070 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201070
Verification of hardware design for data transformation component May 22, 2023 Issued
Array ( [id] => 19259914 [patent_doc_number] => 12019973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Method for reticle enhancement technology of a design pattern to be manufactured on a substrate [patent_app_type] => utility [patent_app_number] => 18/318602 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 10347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318602 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318602
Method for reticle enhancement technology of a design pattern to be manufactured on a substrate May 15, 2023 Issued
Array ( [id] => 19573561 [patent_doc_number] => 20240377853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Power-Efficient Clocking and Clock Shaping [patent_app_type] => utility [patent_app_number] => 18/315074 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315074
Power-Efficient Clocking and Clock Shaping May 9, 2023 Pending
Array ( [id] => 18819863 [patent_doc_number] => 20230394203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 18/310427 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310427
Generating integrated circuit floorplans using neural networks Apr 30, 2023 Issued
Array ( [id] => 19514534 [patent_doc_number] => 20240346220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => ALIGNING MULTI-CHIP DEVICES [patent_app_type] => utility [patent_app_number] => 18/134497 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134497
ALIGNING MULTI-CHIP DEVICES Apr 12, 2023 Pending
Array ( [id] => 18532166 [patent_doc_number] => 20230237238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => AUTOMATED SYSTEM AND METHOD FOR CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/295085 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295085
Automated system and method for circuit design Apr 2, 2023 Issued
Array ( [id] => 19482515 [patent_doc_number] => 20240330557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => TWO BY TWO LOGIC CHIPLET [patent_app_type] => utility [patent_app_number] => 18/128368 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/128368
TWO BY TWO LOGIC CHIPLET Mar 29, 2023 Pending
Array ( [id] => 19467878 [patent_doc_number] => 20240321548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Integrated Circuit with FIB-Ready Structures [patent_app_type] => utility [patent_app_number] => 18/187700 [patent_app_country] => US [patent_app_date] => 2023-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/187700
Integrated Circuit with FIB-Ready Structures Mar 21, 2023 Pending
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