Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10847879 [patent_doc_number] => 08875080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'Programmable macros for metal/via programmable gate array integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/096292 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 3574 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096292
Programmable macros for metal/via programmable gate array integrated circuits Dec 3, 2013 Issued
Array ( [id] => 9398690 [patent_doc_number] => 20140096096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'ANALOG CIRCUIT SIMULATOR AND ANALOG CIRCUIT VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/095142 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3972 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/095142
Analog circuit simulator and analog circuit verification method Dec 2, 2013 Issued
Array ( [id] => 10413558 [patent_doc_number] => 20150298569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'VEHICLE' [patent_app_type] => utility [patent_app_number] => 14/647329 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6369 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14647329 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/647329
Vehicle Nov 25, 2013 Issued
Array ( [id] => 9847818 [patent_doc_number] => 08949752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'System and method of emulating multiple custom prototype boards' [patent_app_type] => utility [patent_app_number] => 14/089522 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089522
System and method of emulating multiple custom prototype boards Nov 24, 2013 Issued
Array ( [id] => 10834849 [patent_doc_number] => 08863045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Optical proximity correction method based on hybrid simulation model' [patent_app_type] => utility [patent_app_number] => 14/086222 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086222 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086222
Optical proximity correction method based on hybrid simulation model Nov 20, 2013 Issued
Array ( [id] => 10401753 [patent_doc_number] => 20150286762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'LOGIC CONFIGURATION METHOD FOR RECONFIGURABLE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/443635 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15426 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443635 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/443635
Logic configuration method for reconfigurable semiconductor device Nov 18, 2013 Issued
Array ( [id] => 9599312 [patent_doc_number] => 20140195993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION' [patent_app_type] => utility [patent_app_number] => 14/081386 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7151 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081386 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081386
Three-dimensional mask model for photolithography simulation Nov 14, 2013 Issued
Array ( [id] => 9871674 [patent_doc_number] => 08959466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-17 [patent_title] => 'Systems and methods for designing layouts for semiconductor device fabrication' [patent_app_type] => utility [patent_app_number] => 14/080222 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080222 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080222
Systems and methods for designing layouts for semiconductor device fabrication Nov 13, 2013 Issued
Array ( [id] => 9460852 [patent_doc_number] => 20140125278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'WIRELESS POWER TRANSMITTER AND WIRELESS POWER RECEIVER' [patent_app_type] => utility [patent_app_number] => 14/075440 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5410 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075440 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/075440
Wireless power transmitter and wireless power receiver Nov 7, 2013 Issued
Array ( [id] => 10645883 [patent_doc_number] => 09362765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-07 [patent_title] => 'Systems and methods for a power adapter for mobile devices' [patent_app_type] => utility [patent_app_number] => 14/075503 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075503 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/075503
Systems and methods for a power adapter for mobile devices Nov 7, 2013 Issued
Array ( [id] => 10503030 [patent_doc_number] => 09231433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Apparatus and method for charging an electrical energy store from an AC voltage source' [patent_app_type] => utility [patent_app_number] => 14/074375 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3178 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074375 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074375
Apparatus and method for charging an electrical energy store from an AC voltage source Nov 6, 2013 Issued
Array ( [id] => 9834616 [patent_doc_number] => 08943450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Model based analog block coverage system' [patent_app_type] => utility [patent_app_number] => 14/052342 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5123 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14052342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/052342
Model based analog block coverage system Oct 10, 2013 Issued
Array ( [id] => 10885697 [patent_doc_number] => 08910101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'Systems and methods for determining effective capacitance to facilitate a timing analysis' [patent_app_type] => utility [patent_app_number] => 14/051522 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14051522 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/051522
Systems and methods for determining effective capacitance to facilitate a timing analysis Oct 10, 2013 Issued
Array ( [id] => 9879127 [patent_doc_number] => 08966424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Methods for cell phasing and placement in dynamic array architecture and implementation of the same' [patent_app_type] => utility [patent_app_number] => 14/040590 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 12424 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040590 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/040590
Methods for cell phasing and placement in dynamic array architecture and implementation of the same Sep 26, 2013 Issued
Array ( [id] => 9934073 [patent_doc_number] => 20150082265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DESIGN STRUCTURE FOR CHIP EXTENSION' [patent_app_type] => utility [patent_app_number] => 14/029902 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4794 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/029902
Structure for chip extension Sep 17, 2013 Issued
Array ( [id] => 10879516 [patent_doc_number] => 08904314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'RC extraction for multiple patterning layout design' [patent_app_type] => utility [patent_app_number] => 14/030672 [patent_app_country] => US [patent_app_date] => 2013-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14030672 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/030672
RC extraction for multiple patterning layout design Sep 17, 2013 Issued
Array ( [id] => 9746630 [patent_doc_number] => 20140282349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD AND APPARATUS FOR CURRENT LIMIT TEST FOR HIGH POWER SWITCHING REGULATOR' [patent_app_type] => utility [patent_app_number] => 14/028792 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5980 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028792 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028792
Method and apparatus for current limit test for high power switching regulator Sep 16, 2013 Issued
Array ( [id] => 9879135 [patent_doc_number] => 08966432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-24 [patent_title] => 'Reduction of jitter in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/019897 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14019897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/019897
Reduction of jitter in an integrated circuit Sep 5, 2013 Issued
Array ( [id] => 9912425 [patent_doc_number] => 20150067629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION' [patent_app_type] => utility [patent_app_number] => 14/015982 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8612 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015982
Diagnosis and debug using truncated simulation Aug 29, 2013 Issued
Array ( [id] => 9899269 [patent_doc_number] => 20150054468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SELF-POWERED INTERNAL MEDICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 13/971306 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7113 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971306
Self-powered internal medical device Aug 19, 2013 Issued
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