Leigh M. Garbowski

Array ( [id] => 9328302 [patent_doc_number] => 20140055084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'CHARGER' [patent_app_type] => utility [patent_app_number] => 13/969826 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7533 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11360662 [patent_doc_number] => 09537325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Battery state estimation system, battery control system, battery system, and battery state estimation method' [patent_app_type] => utility [patent_app_number] => 13/970128 [patent_app_country] => US [patent_app_date] => 2013-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9579036 [patent_doc_number] => 08769473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-01 [patent_title] => 'Wiring design support apparatus, method and computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 13/963482 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10437 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10811196 [patent_doc_number] => 20160157355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'Design Support System, Design Support Method and Design Support Program' [patent_app_type] => utility [patent_app_number] => 14/905358 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6791 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14905358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9163689 [patent_doc_number] => 20130311966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'CIRCUIT DESIGN SUPPORT APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND CIRCUIT DESIGN SUPPORT METHOD' [patent_app_type] => utility [patent_app_number] => 13/948222 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15165 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10175563 [patent_doc_number] => 09205750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Method to estimate battery open-circuit voltage based on transient resistive effects' [patent_app_type] => utility [patent_app_number] => 13/948214 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7128 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10873380 [patent_doc_number] => 08898601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Logic circuit design method, logic circuit design program, and logic circuit design system' [patent_app_type] => utility [patent_app_number] => 13/947302 [patent_app_country] => US [patent_app_date] => 2013-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 7823 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13947302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9291892 [patent_doc_number] => 20140035526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'SELECTIVE COMMUNICATION BASED ON DISTANCE FROM A PLURALITY OF ELECTRIC VEHICLE WIRELESS CHARGING STATIONS IN A FACILITY' [patent_app_type] => utility [patent_app_number] => 13/946875 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17504 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9814096 [patent_doc_number] => 20150026041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'TRANSACTION FLOW CONTROL USING CREDIT AND TOKEN MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/944462 [patent_app_country] => US [patent_app_date] => 2013-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13944462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10867335 [patent_doc_number] => 08893065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Biometric markers in a debugging environment' [patent_app_type] => utility [patent_app_number] => 13/940082 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8986 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13940082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9716940 [patent_doc_number] => 20140252638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'VERTICAL INTERCONNECTS CROSSTALK OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/935940 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10421 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10518026 [patent_doc_number] => 09245076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Orthogonal circuit element routing' [patent_app_type] => utility [patent_app_number] => 13/908562 [patent_app_country] => US [patent_app_date] => 2013-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9500249 [patent_doc_number] => 08739090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Probe signal compression method and apparatus for hardware based verification platforms' [patent_app_type] => utility [patent_app_number] => 13/903672 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6853 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9974373 [patent_doc_number] => 09021411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Characterizing TSV structures in a semiconductor chip stack' [patent_app_type] => utility [patent_app_number] => 13/901332 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9746602 [patent_doc_number] => 20140282321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION' [patent_app_type] => utility [patent_app_number] => 13/864082 [patent_app_country] => US [patent_app_date] => 2013-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1441 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326361 [patent_doc_number] => 08661398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Analysis of stress impact on transistor performance' [patent_app_type] => utility [patent_app_number] => 13/852963 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6003 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9630153 [patent_doc_number] => 08799847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-05 [patent_title] => 'Methods for designing fin-based field effect transistors (FinFETS)' [patent_app_type] => utility [patent_app_number] => 13/838462 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5174 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9291730 [patent_doc_number] => 20140035365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'METHOD OF MEASURING VOLTAGE OF BATTERY PACK AND ENERGY STORAGE SYSTEM INCLUDING THE BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 13/842239 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9006379 [patent_doc_number] => 20130227504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SYSTEM AND METHOD FOR DESIGN, PROCUREMENT AND MANUFACTURING COLLABORATION' [patent_app_type] => utility [patent_app_number] => 13/843730 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9729066 [patent_doc_number] => 20140264773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/841862 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841862 [rel_patent_id] =>[rel_patent_doc_number] =>)