Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9879128 [patent_doc_number] => 08966425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-24 [patent_title] => 'Clock tree generation and routing' [patent_app_type] => utility [patent_app_number] => 13/829512 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 41 [patent_no_of_words] => 15709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829512
Clock tree generation and routing Mar 13, 2013 Issued
Array ( [id] => 9510139 [patent_doc_number] => 20140146630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'DATA TRANSFER ACROSS POWER DOMAINS' [patent_app_type] => utility [patent_app_number] => 13/792592 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6513 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792592 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792592
Data transfer across power domains Mar 10, 2013 Issued
Array ( [id] => 9527692 [patent_doc_number] => 08751983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-10 [patent_title] => 'Method for design partitioning at the behavioral circuit design level' [patent_app_type] => utility [patent_app_number] => 13/789192 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13789192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/789192
Method for design partitioning at the behavioral circuit design level Mar 6, 2013 Issued
Array ( [id] => 9320783 [patent_doc_number] => 20140053121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'ACCELERATOR FOR A READ-CHANNEL DESIGN AND SIMULATION TOOL' [patent_app_type] => utility [patent_app_number] => 13/780222 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780222
Accelerator for a read-channel design and simulation tool Feb 27, 2013 Issued
Array ( [id] => 9688473 [patent_doc_number] => 20140245238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 13/778322 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7644 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13778322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/778322
Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications Feb 26, 2013 Issued
Array ( [id] => 9599316 [patent_doc_number] => 20140195997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/778912 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13778912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/778912
Method and layout of an integrated circuit Feb 26, 2013 Issued
Array ( [id] => 9381386 [patent_doc_number] => 20140084867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'SECONDARY BATTERY DEVICE AND BATTERY CAPACITY ESTIMATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/777093 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777093
SECONDARY BATTERY DEVICE AND BATTERY CAPACITY ESTIMATION SYSTEM Feb 25, 2013 Abandoned
Array ( [id] => 10645890 [patent_doc_number] => 09362772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'System and method for balancing voltages' [patent_app_type] => utility [patent_app_number] => 13/776913 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776913
System and method for balancing voltages Feb 25, 2013 Issued
Array ( [id] => 9444366 [patent_doc_number] => 08713502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Methods and systems to reduce a number of simulations in a timing analysis' [patent_app_type] => utility [patent_app_number] => 13/776892 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776892
Methods and systems to reduce a number of simulations in a timing analysis Feb 25, 2013 Issued
Array ( [id] => 9683118 [patent_doc_number] => 20140239881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'UNIVERSAL BATTERY CHARGER SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/777075 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777075
Universal battery charger system and method Feb 25, 2013 Issued
Array ( [id] => 9683125 [patent_doc_number] => 20140239888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'WIRELESS CHARGER' [patent_app_type] => utility [patent_app_number] => 13/776738 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1229 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776738
WIRELESS CHARGER Feb 25, 2013 Abandoned
Array ( [id] => 9472563 [patent_doc_number] => 08726212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Streamlined parasitic modeling with common device profile' [patent_app_type] => utility [patent_app_number] => 13/773452 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13773452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/773452
Streamlined parasitic modeling with common device profile Feb 20, 2013 Issued
Array ( [id] => 9630145 [patent_doc_number] => 08799838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Equivalence checking method, equivalence checking program, and equivalence checking device' [patent_app_type] => utility [patent_app_number] => 13/769892 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 91 [patent_figures_cnt] => 110 [patent_no_of_words] => 62987 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769892
Equivalence checking method, equivalence checking program, and equivalence checking device Feb 18, 2013 Issued
Array ( [id] => 9652379 [patent_doc_number] => 08806415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Integrated circuit pad modeling' [patent_app_type] => utility [patent_app_number] => 13/768112 [patent_app_country] => US [patent_app_date] => 2013-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13768112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/768112
Integrated circuit pad modeling Feb 14, 2013 Issued
Array ( [id] => 9658898 [patent_doc_number] => 20140229903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'OPTICAL PROXIMITY CORRECTION FOR TOPOGRAPHICALLY NON-UNIFORM SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/763292 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763292
Optical proximity correction for topographically non-uniform substrates Feb 7, 2013 Issued
Array ( [id] => 9714580 [patent_doc_number] => 08839183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Method and apparatus for derived layers visualization and debugging' [patent_app_type] => utility [patent_app_number] => 13/756022 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4929 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756022
Method and apparatus for derived layers visualization and debugging Jan 30, 2013 Issued
Array ( [id] => 9156912 [patent_doc_number] => 08589826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures' [patent_app_type] => utility [patent_app_number] => 13/750963 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4986 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750963 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750963
Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures Jan 24, 2013 Issued
Array ( [id] => 8831869 [patent_doc_number] => 20130132914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Method and Apparatus for Placing Transistors In Proximity to Through-Silicon Vias' [patent_app_type] => utility [patent_app_number] => 13/740439 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740439
Placing transistors in proximity to through-silicon vias Jan 13, 2013 Issued
Array ( [id] => 9611793 [patent_doc_number] => 08788982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Layout design defect repair using inverse lithography' [patent_app_type] => utility [patent_app_number] => 13/740651 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740651
Layout design defect repair using inverse lithography Jan 13, 2013 Issued
Array ( [id] => 9156915 [patent_doc_number] => 08589829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Three-dimensional mask model for photolithography simulation' [patent_app_type] => utility [patent_app_number] => 13/736929 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7215 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736929
Three-dimensional mask model for photolithography simulation Jan 7, 2013 Issued
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