Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9796920 [patent_doc_number] => 20150008864 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2015-01-08 [patent_title] => 'DISTRIBUTED ENERGY STORAGE AND POWER QUALITY CONTROL IN PHOTOVOLTAIC ARRAYS' [patent_app_type] => utility [patent_app_number] => 13/651445 [patent_app_country] => US [patent_app_date] => 2012-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4928 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651445 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/651445
Distributed energy storage and power quality control in photovoltaic arrays Oct 13, 2012 Issued
Array ( [id] => 9796920 [patent_doc_number] => 20150008864 [patent_country] => US [patent_kind] => A2 [patent_issue_date] => 2015-01-08 [patent_title] => 'DISTRIBUTED ENERGY STORAGE AND POWER QUALITY CONTROL IN PHOTOVOLTAIC ARRAYS' [patent_app_type] => utility [patent_app_number] => 13/651445 [patent_app_country] => US [patent_app_date] => 2012-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4928 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651445 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/651445
Distributed energy storage and power quality control in photovoltaic arrays Oct 13, 2012 Issued
Array ( [id] => 8769533 [patent_doc_number] => 20130097570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'METHOD OF INSERTING DUMMY PATTERNS' [patent_app_type] => utility [patent_app_number] => 13/650192 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2524 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/650192
Method of inserting dummy patterns Oct 11, 2012 Issued
Array ( [id] => 9579026 [patent_doc_number] => 08769462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Parasitic extraction for semiconductors' [patent_app_type] => utility [patent_app_number] => 13/646612 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5350 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646612
Parasitic extraction for semiconductors Oct 4, 2012 Issued
Array ( [id] => 9386391 [patent_doc_number] => 20140089874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'Method and Apparatus for Optimizing Memory-Built-In-Self Test' [patent_app_type] => utility [patent_app_number] => 13/625682 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11079 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625682
Method and apparatus for optimizing memory-built-in-self test Sep 23, 2012 Issued
Array ( [id] => 8824026 [patent_doc_number] => 20130125071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'CIRCUIT COMPONENT MIGRATION APPARATUS, CIRCUIT COMPONENT MIGRATION PROGRAM, AND CIRCUIT COMPONENT MIGRATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/624136 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9235 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624136 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/624136
Circuit component migration method and apparatus Sep 20, 2012 Issued
Array ( [id] => 9006376 [patent_doc_number] => 20130227500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Calculation System For Inverse Masks' [patent_app_type] => utility [patent_app_number] => 13/623106 [patent_app_country] => US [patent_app_date] => 2012-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 22724 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13623106 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/623106
Calculation System For Inverse Masks Sep 18, 2012 Abandoned
Array ( [id] => 9358734 [patent_doc_number] => 08677289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Method of generating assistant feature' [patent_app_type] => utility [patent_app_number] => 13/615632 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2289 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/615632
Method of generating assistant feature Sep 13, 2012 Issued
Array ( [id] => 9116330 [patent_doc_number] => 08572522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Illumination-source shape definition in optical lithography' [patent_app_type] => utility [patent_app_number] => 13/618562 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9210 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/618562
Illumination-source shape definition in optical lithography Sep 13, 2012 Issued
Array ( [id] => 9000895 [patent_doc_number] => 20130222019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/596252 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/596252
SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT Aug 27, 2012 Abandoned
Array ( [id] => 9358733 [patent_doc_number] => 08677288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Test pattern selection method for OPC model calibration' [patent_app_type] => utility [patent_app_number] => 13/594492 [patent_app_country] => US [patent_app_date] => 2012-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3727 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13594492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/594492
Test pattern selection method for OPC model calibration Aug 23, 2012 Issued
Array ( [id] => 8686904 [patent_doc_number] => 20130055188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'SEMICONDUCTOR LAYOUT SETTING DEVICE, SEMICONDUCTOR LAYOUT SETTING METHOD, AND SEMICONDUCTOR LAYOUT SETTING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/593192 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 10865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593192 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593192
SEMICONDUCTOR LAYOUT SETTING DEVICE, SEMICONDUCTOR LAYOUT SETTING METHOD, AND SEMICONDUCTOR LAYOUT SETTING PROGRAM Aug 22, 2012 Abandoned
Array ( [id] => 9248596 [patent_doc_number] => 08612898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-17 [patent_title] => 'Identification of illegal devices using contact mapping' [patent_app_type] => utility [patent_app_number] => 13/585152 [patent_app_country] => US [patent_app_date] => 2012-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2828 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585152 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/585152
Identification of illegal devices using contact mapping Aug 13, 2012 Issued
Array ( [id] => 9404876 [patent_doc_number] => 08694941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'System and method for abutment in the presence of dummy shapes' [patent_app_type] => utility [patent_app_number] => 13/570942 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4666 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/570942
System and method for abutment in the presence of dummy shapes Aug 8, 2012 Issued
Array ( [id] => 9218549 [patent_doc_number] => 08631359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'System and technique for modeling resist profile change sensitivity at different heights' [patent_app_type] => utility [patent_app_number] => 13/569162 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13569162 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/569162
System and technique for modeling resist profile change sensitivity at different heights Aug 6, 2012 Issued
Array ( [id] => 10732003 [patent_doc_number] => 20160078153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SUBTHRESHOLD STANDARD CELL LOGIC LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/564902 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1384 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564902
SUBTHRESHOLD STANDARD CELL LOGIC LIBRARY Aug 1, 2012 Abandoned
Array ( [id] => 8639720 [patent_doc_number] => 20130031524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 13/559612 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5516 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13559612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/559612
ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS Jul 26, 2012 Abandoned
Array ( [id] => 9187246 [patent_doc_number] => 08627247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Systems and methods for fixing pin mismatch in layout migration' [patent_app_type] => utility [patent_app_number] => 13/546562 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546562
Systems and methods for fixing pin mismatch in layout migration Jul 10, 2012 Issued
Array ( [id] => 8474434 [patent_doc_number] => 20120273841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same' [patent_app_type] => utility [patent_app_number] => 13/540529 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12316 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540529 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/540529
Methods for cell phasing and placement in dynamic array architecture and implementation of the same Jul 1, 2012 Issued
Array ( [id] => 8462625 [patent_doc_number] => 20120267794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/535412 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3851 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535412 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535412
Structure and design structure for high-Q value inductor and method of manufacturing the same Jun 27, 2012 Issued
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