Leigh M. Garbowski

Array ( [id] => 9229884 [patent_doc_number] => 08635566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Parity error detection verification' [patent_app_type] => utility [patent_app_number] => 13/331172 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3867 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9029823 [patent_doc_number] => 08539421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Layout-specific classification and prioritization of recommended rules violations' [patent_app_type] => utility [patent_app_number] => 13/328942 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13328942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10937027 [patent_doc_number] => 20140340048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'FACILITY INFORMATION PRESENTATION DEVICE AND FACILITY INFORMATION PRESENTATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/365110 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14365110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9044356 [patent_doc_number] => 20130246994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'WIRING CHECK DEVICE AND WIRING CHECK SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/988882 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12011 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13988882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9781480 [patent_doc_number] => 08856704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Layout library of flip-flop circuit' [patent_app_type] => utility [patent_app_number] => 13/989052 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8458 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13989052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8805032 [patent_doc_number] => 08443316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-14 [patent_title] => 'Accelerating coverage convergence and debug using symbolic properties and local multi-path analysis' [patent_app_type] => utility [patent_app_number] => 13/293032 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5046 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10141752 [patent_doc_number] => 09174544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Method for charging a battery for supplying power to a drive motor of a motor vehicle' [patent_app_type] => utility [patent_app_number] => 13/883072 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2821 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787175 [patent_doc_number] => 08434031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Inverse mask design and correction for electronic design' [patent_app_type] => utility [patent_app_number] => 13/283523 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 86 [patent_no_of_words] => 24976 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787175 [patent_doc_number] => 08434031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Inverse mask design and correction for electronic design' [patent_app_type] => utility [patent_app_number] => 13/283523 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 86 [patent_no_of_words] => 24976 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787175 [patent_doc_number] => 08434031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Inverse mask design and correction for electronic design' [patent_app_type] => utility [patent_app_number] => 13/283523 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 86 [patent_no_of_words] => 24976 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787175 [patent_doc_number] => 08434031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Inverse mask design and correction for electronic design' [patent_app_type] => utility [patent_app_number] => 13/283523 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 86 [patent_no_of_words] => 24976 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8162776 [patent_doc_number] => 20120102443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'N/P CONFIGURABLE LDMOS SUBCIRCUIT MACRO MODEL' [patent_app_type] => utility [patent_app_number] => 13/277932 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5447 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102443.pdf [firstpage_image] =>[orig_patent_app_number] => 13277932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8985294 [patent_doc_number] => 08516424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Timing signoff system and method that takes static and dynamic voltage drop into account' [patent_app_type] => utility [patent_app_number] => 13/246102 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13246102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8998266 [patent_doc_number] => 08522172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method of forming photomask using calibration pattern, and photomask having calibration pattern' [patent_app_type] => utility [patent_app_number] => 13/240732 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8935820 [patent_doc_number] => 08495542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Automated management of verification waivers' [patent_app_type] => utility [patent_app_number] => 13/234952 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5057 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8837305 [patent_doc_number] => 08453075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Automated lithographic hot spot detection employing unsupervised topological image categorization' [patent_app_type] => utility [patent_app_number] => 13/224402 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8023003 [patent_doc_number] => 08141021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Combined memories in integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/224173 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141021.pdf [firstpage_image] =>[orig_patent_app_number] => 13224173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8189482 [patent_doc_number] => 20120117529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'APPARATUS, DESIGN METHOD AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/221572 [patent_app_country] => US [patent_app_date] => 2011-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 11492 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117529.pdf [firstpage_image] =>[orig_patent_app_number] => 13221572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7580380 [patent_doc_number] => 20110294263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Pattern verification method, program thereof, and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/067567 [patent_app_country] => US [patent_app_date] => 2011-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20110294263.pdf [firstpage_image] =>[orig_patent_app_number] => 13067567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8449281 [patent_doc_number] => 08291351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Intelligent pattern signature based on lithography effects' [patent_app_type] => utility [patent_app_number] => 13/151208 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2833 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151208 [rel_patent_id] =>[rel_patent_doc_number] =>)