Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8504732 [patent_doc_number] => 20120304140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'FULLY PARAMETERIZABLE REPRESENTATION OF A HIGHER LEVEL DESIGN ENTITY' [patent_app_type] => utility [patent_app_number] => 13/114834 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2658 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13114834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/114834
Fully parameterizable representation of a higher level design entity May 23, 2011 Issued
Array ( [id] => 6169870 [patent_doc_number] => 20110175144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings' [patent_app_type] => utility [patent_app_number] => 13/073994 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 77 [patent_no_of_words] => 35192 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175144.pdf [firstpage_image] =>[orig_patent_app_number] => 13073994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073994
Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings Mar 27, 2011 Issued
Array ( [id] => 8633002 [patent_doc_number] => 08365101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures' [patent_app_type] => utility [patent_app_number] => 13/050250 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050250 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050250
Photomask constructions having liners of specified compositions along sidewalls of multi-layered structures Mar 16, 2011 Issued
Array ( [id] => 8899594 [patent_doc_number] => 08479128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Technique for honoring multi-cycle path semantics in RTL simulation' [patent_app_type] => utility [patent_app_number] => 13/039982 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3446 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039982 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039982
Technique for honoring multi-cycle path semantics in RTL simulation Mar 2, 2011 Issued
Array ( [id] => 10093373 [patent_doc_number] => 09130205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Controlling PEM fuel cell voltage during power transitions and idling' [patent_app_type] => utility [patent_app_number] => 13/261721 [patent_app_country] => US [patent_app_date] => 2011-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5869 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13261721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/261721
Controlling PEM fuel cell voltage during power transitions and idling Feb 24, 2011 Issued
Array ( [id] => 8038005 [patent_doc_number] => 20120068736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'DESIGN APPARATUS, DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/032506 [patent_app_country] => US [patent_app_date] => 2011-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068736.pdf [firstpage_image] =>[orig_patent_app_number] => 13032506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/032506
DESIGN APPARATUS, DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT Feb 21, 2011 Abandoned
Array ( [id] => 7813746 [patent_doc_number] => 20120060366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'METHOD FOR DETERMINING WIRING PATHWAY OF WIRING BOARD AND METHOD FOR DETERMINING WIRING PATHWAY OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/029972 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8187 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20120060366.pdf [firstpage_image] =>[orig_patent_app_number] => 13029972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029972
METHOD FOR DETERMINING WIRING PATHWAY OF WIRING BOARD AND METHOD FOR DETERMINING WIRING PATHWAY OF SEMICONDUCTOR DEVICE Feb 16, 2011 Abandoned
Array ( [id] => 9555852 [patent_doc_number] => 08762925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'MEMS modeling system and method' [patent_app_type] => utility [patent_app_number] => 13/029942 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13029942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029942
MEMS modeling system and method Feb 16, 2011 Issued
Array ( [id] => 8507043 [patent_doc_number] => 20120306451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'SECONDARY CELL PROTECTION CIRCUIT AND BATTERY' [patent_app_type] => utility [patent_app_number] => 13/578781 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7332 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578781 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/578781
Secondary cell protection circuit and battery Feb 14, 2011 Issued
Array ( [id] => 8849438 [patent_doc_number] => 08458638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Cell library, integrated circuit, and methods of making same' [patent_app_type] => utility [patent_app_number] => 13/023172 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13023172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023172
Cell library, integrated circuit, and methods of making same Feb 7, 2011 Issued
Array ( [id] => 7495209 [patent_doc_number] => 08032846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Efficient provisioning of resources in public infrastructure for electronic design automation (EDA) tasks' [patent_app_type] => utility [patent_app_number] => 13/016712 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032846.pdf [firstpage_image] =>[orig_patent_app_number] => 13016712 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016712
Efficient provisioning of resources in public infrastructure for electronic design automation (EDA) tasks Jan 27, 2011 Issued
Array ( [id] => 9555841 [patent_doc_number] => 08762914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness' [patent_app_type] => utility [patent_app_number] => 12/982732 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6245 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982732
Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness Dec 29, 2010 Issued
Array ( [id] => 8985276 [patent_doc_number] => 08516406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing' [patent_app_type] => utility [patent_app_number] => 12/982712 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 16 [patent_no_of_words] => 14084 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982712
Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing Dec 29, 2010 Issued
Array ( [id] => 8655580 [patent_doc_number] => 08375348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method, system, and program product to implement colored tiles for detail routing for double pattern lithography' [patent_app_type] => utility [patent_app_number] => 12/981062 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8686 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981062
Method, system, and program product to implement colored tiles for detail routing for double pattern lithography Dec 28, 2010 Issued
Array ( [id] => 11249912 [patent_doc_number] => 09475400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Charging device and methods for controlling a charging device' [patent_app_type] => utility [patent_app_number] => 13/992525 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992525
Charging device and methods for controlling a charging device Dec 9, 2010 Issued
Array ( [id] => 8985270 [patent_doc_number] => 08516400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method for predicting tolerable spacing between conductors in semiconductor process' [patent_app_type] => utility [patent_app_number] => 12/941652 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12941652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941652
Method for predicting tolerable spacing between conductors in semiconductor process Nov 7, 2010 Issued
Array ( [id] => 8172537 [patent_doc_number] => 20120107969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES' [patent_app_type] => utility [patent_app_number] => 12/914212 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20120107969.pdf [firstpage_image] =>[orig_patent_app_number] => 12914212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914212
Method and system for comparing lithographic processing conditions and or data preparation processes Oct 27, 2010 Issued
Array ( [id] => 7756712 [patent_doc_number] => 08112736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Differential voltage defectivity monitoring method' [patent_app_type] => utility [patent_app_number] => 12/896869 [patent_app_country] => US [patent_app_date] => 2010-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6909 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112736.pdf [firstpage_image] =>[orig_patent_app_number] => 12896869 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/896869
Differential voltage defectivity monitoring method Oct 1, 2010 Issued
Array ( [id] => 5989420 [patent_doc_number] => 20110012260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/892273 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 20960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012260.pdf [firstpage_image] =>[orig_patent_app_number] => 12892273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892273
METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT Sep 27, 2010 Abandoned
Array ( [id] => 7819910 [patent_doc_number] => 20120066530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Configurable Power Switch Cells and Methodology' [patent_app_type] => utility [patent_app_number] => 12/879772 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10262 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066530.pdf [firstpage_image] =>[orig_patent_app_number] => 12879772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879772
Configurable power switch cells and methodology Sep 9, 2010 Issued
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