Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8438331 [patent_doc_number] => 08286116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-09 [patent_title] => 'Composite wire indexing for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/871764 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12871764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871764
Composite wire indexing for programmable logic devices Aug 29, 2010 Issued
Array ( [id] => 8262256 [patent_doc_number] => 20120161677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'BATTERY MODULE, BATTERY SYSTEM AND ELECTRICALLY DRIVEN VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/393527 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23706 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13393527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/393527
BATTERY MODULE, BATTERY SYSTEM AND ELECTRICALLY DRIVEN VEHICLE Aug 26, 2010 Abandoned
Array ( [id] => 7785219 [patent_doc_number] => 20120046775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'METHOD FOR ENHANCING WAFER EXPOSURE EFFECTIVENESS AND EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 12/860572 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5091 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20120046775.pdf [firstpage_image] =>[orig_patent_app_number] => 12860572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860572
Method for enhancing wafer exposure effectiveness and efficiency Aug 19, 2010 Issued
Array ( [id] => 8595016 [patent_doc_number] => 08352899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method to modify an integrated circuit (IC) design' [patent_app_type] => utility [patent_app_number] => 12/860662 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12860662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/860662
Method to modify an integrated circuit (IC) design Aug 19, 2010 Issued
Array ( [id] => 8805029 [patent_doc_number] => 08443313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Circuit design optimization' [patent_app_type] => utility [patent_app_number] => 12/858522 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8398 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12858522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858522
Circuit design optimization Aug 17, 2010 Issued
Array ( [id] => 8763383 [patent_doc_number] => 08423922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Photomask designing method and photomask designing program' [patent_app_type] => utility [patent_app_number] => 12/850082 [patent_app_country] => US [patent_app_date] => 2010-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12850082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/850082
Photomask designing method and photomask designing program Aug 3, 2010 Issued
Array ( [id] => 8752273 [patent_doc_number] => 08418117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Chip-level ECO shrink' [patent_app_type] => utility [patent_app_number] => 12/831982 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3858 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12831982 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831982
Chip-level ECO shrink Jul 6, 2010 Issued
Array ( [id] => 8881396 [patent_doc_number] => 20130154580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'APPARATUS FOR CHARGING THIN-FILM CAPACITORS' [patent_app_type] => utility [patent_app_number] => 13/807900 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1421 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13807900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/807900
APPARATUS FOR CHARGING THIN-FILM CAPACITORS Jun 30, 2010 Abandoned
Array ( [id] => 8561938 [patent_doc_number] => 08336009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Method and apparatus for electronic system function verification at two levels' [patent_app_type] => utility [patent_app_number] => 12/827012 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827012
Method and apparatus for electronic system function verification at two levels Jun 29, 2010 Issued
Array ( [id] => 8558316 [patent_doc_number] => 08332803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-11 [patent_title] => 'Method and apparatus for integrated circuit package thermo-mechanical reliability analysis' [patent_app_type] => utility [patent_app_number] => 12/824542 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824542
Method and apparatus for integrated circuit package thermo-mechanical reliability analysis Jun 27, 2010 Issued
Array ( [id] => 8536246 [patent_doc_number] => 08312412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Support apparatus and design support method' [patent_app_type] => utility [patent_app_number] => 12/825112 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3704 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12825112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825112
Support apparatus and design support method Jun 27, 2010 Issued
Array ( [id] => 7563102 [patent_doc_number] => 20110276936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'METHOD FOR ANALOG PLACEMENT AND GLOBAL ROUTING CONSIDERING WIRING SYMMETRY' [patent_app_type] => utility [patent_app_number] => 12/824942 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3317 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276936.pdf [firstpage_image] =>[orig_patent_app_number] => 12824942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824942
Method for analog placement and global routing considering wiring symmetry Jun 27, 2010 Issued
Array ( [id] => 8849430 [patent_doc_number] => 08458630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'Supporting dynamic aspects of polymorphism in high-level synthesis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/824152 [patent_app_country] => US [patent_app_date] => 2010-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8689 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824152
Supporting dynamic aspects of polymorphism in high-level synthesis of integrated circuit designs Jun 25, 2010 Issued
Array ( [id] => 8655576 [patent_doc_number] => 08375344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method and system for determining configurations' [patent_app_type] => utility [patent_app_number] => 12/824042 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7770 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824042
Method and system for determining configurations Jun 24, 2010 Issued
Array ( [id] => 8461029 [patent_doc_number] => 08296715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Wiring design assisting apparatus, wiring design assisting method, and computer-readable information recording medium' [patent_app_type] => utility [patent_app_number] => 12/823222 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 17593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823222
Wiring design assisting apparatus, wiring design assisting method, and computer-readable information recording medium Jun 24, 2010 Issued
Array ( [id] => 7671723 [patent_doc_number] => 20110320992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/823232 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9853 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823232 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823232
Buffer-aware routing in integrated circuit design Jun 24, 2010 Issued
Array ( [id] => 7671728 [patent_doc_number] => 20110320997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Delay-Cell Footprint-Compatible Buffers' [patent_app_type] => utility [patent_app_number] => 12/822272 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2130 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822272
Delay-Cell Footprint-Compatible Buffers Jun 23, 2010 Abandoned
Array ( [id] => 8343242 [patent_doc_number] => 08245181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Printed circuit board layout system and method thereof' [patent_app_type] => utility [patent_app_number] => 12/813522 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1969 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12813522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/813522
Printed circuit board layout system and method thereof Jun 10, 2010 Issued
Array ( [id] => 6006215 [patent_doc_number] => 20110119544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'User Guided Short Correction And Schematic Fix Visualization' [patent_app_type] => utility [patent_app_number] => 12/797602 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10655 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119544.pdf [firstpage_image] =>[orig_patent_app_number] => 12797602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797602
User Guided Short Correction And Schematic Fix Visualization Jun 8, 2010 Abandoned
Array ( [id] => 7653277 [patent_doc_number] => 20110302546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION' [patent_app_type] => utility [patent_app_number] => 12/795592 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11695 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302546.pdf [firstpage_image] =>[orig_patent_app_number] => 12795592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/795592
Performing scenario reduction Jun 6, 2010 Issued
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