Leigh M. Garbowski

Array ( [id] => 6474992 [patent_doc_number] => 20100207655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip' [patent_app_type] => utility [patent_app_number] => 12/772803 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3109 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20100207655.pdf [firstpage_image] =>[orig_patent_app_number] => 12772803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7682406 [patent_doc_number] => 20100242005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'System and method for design, procurement and manufacturing collaboration' [patent_app_type] => utility [patent_app_number] => 12/799534 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20100242005.pdf [firstpage_image] =>[orig_patent_app_number] => 12799534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8449288 [patent_doc_number] => 08291358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Synchronous to asynchronous logic conversion' [patent_app_type] => utility [patent_app_number] => 12/768129 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12768129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220458 [patent_doc_number] => 08196087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Chip area optimized pads' [patent_app_type] => utility [patent_app_number] => 12/760442 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196087.pdf [firstpage_image] =>[orig_patent_app_number] => 12760442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9218558 [patent_doc_number] => 08631368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Method and circuit to generate race condition test data at multiple supply voltages' [patent_app_type] => utility [patent_app_number] => 12/749602 [patent_app_country] => US [patent_app_date] => 2010-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14429 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12749602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8391236 [patent_doc_number] => 20120229084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'SYSTEM AND METHOD FOR COMPATIBLE WIRED CHARGING AND WIRELESS CHARGING' [patent_app_type] => utility [patent_app_number] => 13/509961 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3460 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6396181 [patent_doc_number] => 20100164560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/721776 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10977 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164560.pdf [firstpage_image] =>[orig_patent_app_number] => 12721776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8595002 [patent_doc_number] => 08352885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Three-dimensional mask model for photolithography simulation' [patent_app_type] => utility [patent_app_number] => 12/721343 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7205 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12721343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6100651 [patent_doc_number] => 20110004856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'Inverse Mask Design and Correction for Electronic Design' [patent_app_type] => utility [patent_app_number] => 12/710352 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 24859 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004856.pdf [firstpage_image] =>[orig_patent_app_number] => 12710352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6358243 [patent_doc_number] => 20100250224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'POWER SOURCE NOISE ANALYSIS DEVICE AND ANALYSIS METHOD' [patent_app_type] => utility [patent_app_number] => 12/640472 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5956 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250224.pdf [firstpage_image] =>[orig_patent_app_number] => 12640472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6652429 [patent_doc_number] => 20100229137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'System and Method for Performance Modeling of Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 12/630712 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229137.pdf [firstpage_image] =>[orig_patent_app_number] => 12630712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8389151 [patent_doc_number] => 08266563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Multi-mode redundancy removal' [patent_app_type] => utility [patent_app_number] => 12/625392 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4752 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12625392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6535408 [patent_doc_number] => 20100218159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Data Flow Branching in Mask Data Preparation' [patent_app_type] => utility [patent_app_number] => 12/622402 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3761 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218159.pdf [firstpage_image] =>[orig_patent_app_number] => 12622402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8033871 [patent_doc_number] => 08146026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Simultaneous photolithographic mask and target optimization' [patent_app_type] => utility [patent_app_number] => 12/619742 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146026.pdf [firstpage_image] =>[orig_patent_app_number] => 12619742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8297467 [patent_doc_number] => 08225269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Technique for generating an analysis equation' [patent_app_type] => utility [patent_app_number] => 12/609572 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12609572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5933072 [patent_doc_number] => 20110041112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING A CENTERLINE CONNECTIVITY REPRESENTATION' [patent_app_type] => utility [patent_app_number] => 12/605272 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7801 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20110041112.pdf [firstpage_image] =>[orig_patent_app_number] => 12605272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6621603 [patent_doc_number] => 20100064268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Capacitor arrangement method and layout apparatus' [patent_app_type] => utility [patent_app_number] => 12/588102 [patent_app_country] => US [patent_app_date] => 2009-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2544 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064268.pdf [firstpage_image] =>[orig_patent_app_number] => 12588102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7993371 [patent_doc_number] => 08078994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method of designing semiconductor device including density verification' [patent_app_type] => utility [patent_app_number] => 12/556302 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4014 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078994.pdf [firstpage_image] =>[orig_patent_app_number] => 12556302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4606449 [patent_doc_number] => 07987435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Pattern verification method, program thereof, and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/585073 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5889 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987435.pdf [firstpage_image] =>[orig_patent_app_number] => 12585073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8837310 [patent_doc_number] => 08453079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Automated conversion of synchronous to asynchronous circuit design representations' [patent_app_type] => utility [patent_app_number] => 12/550582 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5891 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12550582 [rel_patent_id] =>[rel_patent_doc_number] =>)