Search

Leigh M. Garbowski

Examiner (ID: 19623, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2851, 2304, 2763
Total Applications
1722
Issued Applications
1536
Pending Applications
76
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19451407 [patent_doc_number] => 20240311537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Systems And Methods For Generating Redacted Circuit Designs For Integrated Circuits [patent_app_type] => utility [patent_app_number] => 18/120857 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120857
Systems And Methods For Generating Redacted Circuit Designs For Integrated Circuits Mar 12, 2023 Pending
Array ( [id] => 19436635 [patent_doc_number] => 20240305133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Resetting Quantum States of Multi-State Devices Via Tunable Energy-Transfer Devices Within Quantum Computing Systems [patent_app_type] => utility [patent_app_number] => 18/180743 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180743
Resetting Quantum States of Multi-State Devices Via Tunable Energy-Transfer Devices Within Quantum Computing Systems Mar 7, 2023 Pending
Array ( [id] => 18957690 [patent_doc_number] => 20240046017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ARITHMETIC METHOD AND ARITHMETIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/180803 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180803
ARITHMETIC METHOD AND ARITHMETIC DEVICE Mar 7, 2023 Pending
Array ( [id] => 18584993 [patent_doc_number] => 20230267257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => AUTOMATED VERIFICATION OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/177065 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177065
AUTOMATED VERIFICATION OF INTEGRATED CIRCUITS Feb 28, 2023 Pending
Array ( [id] => 18847545 [patent_doc_number] => 20230409949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => QUANTUM COMPUTER AND CONTROL METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/115388 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115388
QUANTUM COMPUTER AND CONTROL METHOD THEREFOR Feb 27, 2023 Pending
Array ( [id] => 19391714 [patent_doc_number] => 20240281584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => PHYSICAL LAYOUT SYNTHESIS FOR STANDARD CELLS USING SLICE LAYOUTS [patent_app_type] => utility [patent_app_number] => 18/170335 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170335
PHYSICAL LAYOUT SYNTHESIS FOR STANDARD CELLS USING SLICE LAYOUTS Feb 15, 2023 Pending
Array ( [id] => 20624217 [patent_doc_number] => 12591725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Automated synthesis of virtual system-on-chip environments [patent_app_type] => utility [patent_app_number] => 18/170316 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170316
Automated synthesis of virtual system-on-chip environments Feb 15, 2023 Issued
Array ( [id] => 19269399 [patent_doc_number] => 20240213103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DEVICE AND METHOD FOR SEMICONDUCTOR CHIP ASSISTANCE DESIGN AND METHOD FOR CONSTRUCTING CHIP CHARACTERISTICS MODEL [patent_app_type] => utility [patent_app_number] => 18/168574 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168574
DEVICE AND METHOD FOR SEMICONDUCTOR CHIP ASSISTANCE DESIGN AND METHOD FOR CONSTRUCTING CHIP CHARACTERISTICS MODEL Feb 13, 2023 Pending
Array ( [id] => 18856094 [patent_doc_number] => 11853678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Block level design method for heterogeneous PG-structure cells [patent_app_type] => utility [patent_app_number] => 18/096906 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096906
Block level design method for heterogeneous PG-structure cells Jan 12, 2023 Issued
Array ( [id] => 18637099 [patent_doc_number] => 11761688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Solar integrated chiller method and system [patent_app_type] => utility [patent_app_number] => 18/096268 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 1926 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096268
Solar integrated chiller method and system Jan 11, 2023 Issued
Array ( [id] => 18361345 [patent_doc_number] => 20230142936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MODELLING AND PREDICTION SYSTEM WITH AUTO MACHINE LEARNING IN THE PRODUCTION OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/152669 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152669
Modelling and prediction system with auto machine learning in the production of memory devices Jan 9, 2023 Issued
Array ( [id] => 19303904 [patent_doc_number] => 20240232484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => CHIP STRUCTURE WITH STEGANOGRAPHIC FILL SHAPE PATTERN [patent_app_type] => utility [patent_app_number] => 18/152707 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152707
Chip structure with steganographic fill shape pattern Jan 9, 2023 Issued
Array ( [id] => 19137230 [patent_doc_number] => 11972194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Method for determining patterning device pattern based on manufacturability [patent_app_type] => utility [patent_app_number] => 18/089848 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 19101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089848 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089848
Method for determining patterning device pattern based on manufacturability Dec 27, 2022 Issued
Array ( [id] => 20331177 [patent_doc_number] => 12461450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => OPC modeling method [patent_app_type] => utility [patent_app_number] => 18/076814 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076814 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076814
OPC modeling method Dec 6, 2022 Issued
Array ( [id] => 20636073 [patent_doc_number] => 12596949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Method and apparatus for linear optical quantum computing [patent_app_type] => utility [patent_app_number] => 18/075327 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 11559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075327
Method and apparatus for linear optical quantum computing Dec 4, 2022 Issued
Array ( [id] => 19933340 [patent_doc_number] => 12306543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Optical imaging method, device and system for photolithography system [patent_app_type] => utility [patent_app_number] => 17/993715 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2391 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/993715
Optical imaging method, device and system for photolithography system Nov 22, 2022 Issued
Array ( [id] => 20316952 [patent_doc_number] => 12455502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Device and method for generating photomasks [patent_app_type] => utility [patent_app_number] => 17/983972 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 1115 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17983972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/983972
Device and method for generating photomasks Nov 8, 2022 Issued
Array ( [id] => 20883781 [patent_doc_number] => 12699824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Determining substrate characteristics by virtual substrate measurement [patent_app_type] => utility [patent_app_number] => 17/982157 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982157
DETERMINING SUBSTRATE CHARACTERISTICS BY VIRTUAL SUBSTRATE MEASUREMENT Nov 6, 2022 Pending
Array ( [id] => 19144942 [patent_doc_number] => 20240143878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => DELAY CALCULATION WITH PATTERN MATCHING FOR STATIC TIMING ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/977809 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977809
DELAY CALCULATION WITH PATTERN MATCHING FOR STATIC TIMING ANALYSIS Oct 30, 2022 Pending
Array ( [id] => 19144954 [patent_doc_number] => 20240143890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => Smart Scan Options to Improve Wafer Die Yield [patent_app_type] => utility [patent_app_number] => 18/050151 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18050151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/050151
Smart scan options to improve wafer die yield Oct 26, 2022 Issued
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