Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5399898 [patent_doc_number] => 20090319961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Method of Verification of Address Translation Mechanisms' [patent_app_type] => utility [patent_app_number] => 12/550419 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8301 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319961.pdf [firstpage_image] =>[orig_patent_app_number] => 12550419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550419
Method of verification of address translation mechanisms Aug 30, 2009 Issued
Array ( [id] => 6263476 [patent_doc_number] => 20100031219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'APPARATUS, METHOD, AND PROGRAM FOR PREDICTING LAYOUT WIRING CONGESTION' [patent_app_type] => utility [patent_app_number] => 12/511452 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3981 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031219.pdf [firstpage_image] =>[orig_patent_app_number] => 12511452 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511452
Apparatus, method, and program for predicting layout wiring congestion Jul 28, 2009 Issued
Array ( [id] => 6154285 [patent_doc_number] => 20110022996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS' [patent_app_type] => utility [patent_app_number] => 12/510122 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022996.pdf [firstpage_image] =>[orig_patent_app_number] => 12510122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510122
Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods Jul 26, 2009 Issued
Array ( [id] => 7780296 [patent_doc_number] => 08122422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor' [patent_app_type] => utility [patent_app_number] => 12/510082 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122422.pdf [firstpage_image] =>[orig_patent_app_number] => 12510082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510082
Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor Jul 26, 2009 Issued
Array ( [id] => 5554062 [patent_doc_number] => 20090288048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 12/510187 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5967 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20090288048.pdf [firstpage_image] =>[orig_patent_app_number] => 12510187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510187
Analysis of stress impact on transistor performance Jul 26, 2009 Issued
Array ( [id] => 7532707 [patent_doc_number] => 07844941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Charged particle beam exposure method and charged particle beam exposure device' [patent_app_type] => utility [patent_app_number] => 12/508642 [patent_app_country] => US [patent_app_date] => 2009-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4515 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844941.pdf [firstpage_image] =>[orig_patent_app_number] => 12508642 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/508642
Charged particle beam exposure method and charged particle beam exposure device Jul 23, 2009 Issued
Array ( [id] => 4488908 [patent_doc_number] => 07908573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Minimizing effects of interconnect variations in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/505357 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11659 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908573.pdf [firstpage_image] =>[orig_patent_app_number] => 12505357 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/505357
Minimizing effects of interconnect variations in integrated circuit designs Jul 16, 2009 Issued
Array ( [id] => 6352812 [patent_doc_number] => 20100072614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => '3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD' [patent_app_type] => utility [patent_app_number] => 12/504272 [patent_app_country] => US [patent_app_date] => 2009-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3620 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20100072614.pdf [firstpage_image] =>[orig_patent_app_number] => 12504272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/504272
3-dimensional integrated circuit designing method Jul 15, 2009 Issued
Array ( [id] => 5560176 [patent_doc_number] => 20090271753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same' [patent_app_type] => utility [patent_app_number] => 12/497052 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12249 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271753.pdf [firstpage_image] =>[orig_patent_app_number] => 12497052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497052
Methods for cell phasing and placement in dynamic array architecture and implementation of the same Jul 1, 2009 Issued
Array ( [id] => 6566513 [patent_doc_number] => 20100017776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'DESIGN PROGRAM, DESIGN APPARATUS, AND DESIGN METHOD FOR DYNAMIC RECONFIGURABLE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/497022 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 12164 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017776.pdf [firstpage_image] =>[orig_patent_app_number] => 12497022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497022
Program, design apparatus, and design method for dynamic reconfigurable circuit Jul 1, 2009 Issued
Array ( [id] => 8343248 [patent_doc_number] => 08245180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same' [patent_app_type] => utility [patent_app_number] => 12/484130 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 13649 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12484130 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484130
Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same Jun 11, 2009 Issued
Array ( [id] => 8297439 [patent_doc_number] => 08225239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Methods for defining and utilizing sub-resolution features in linear topology' [patent_app_type] => utility [patent_app_number] => 12/479674 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12814 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12479674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479674
Methods for defining and utilizing sub-resolution features in linear topology Jun 4, 2009 Issued
Array ( [id] => 4550782 [patent_doc_number] => 07873928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Hierarchical analog IC placement subject to symmetry, matching and proximity constraints' [patent_app_type] => utility [patent_app_number] => 12/472323 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 68 [patent_no_of_words] => 12798 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/873/07873928.pdf [firstpage_image] =>[orig_patent_app_number] => 12472323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472323
Hierarchical analog IC placement subject to symmetry, matching and proximity constraints May 25, 2009 Issued
Array ( [id] => 8149419 [patent_doc_number] => 08166436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Early logic mapper during FPGA synthesis' [patent_app_type] => utility [patent_app_number] => 12/430757 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3001 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166436.pdf [firstpage_image] =>[orig_patent_app_number] => 12430757 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430757
Early logic mapper during FPGA synthesis Apr 26, 2009 Issued
Array ( [id] => 5529071 [patent_doc_number] => 20090199148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Pattern-producing method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/385454 [patent_app_country] => US [patent_app_date] => 2009-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3999 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199148.pdf [firstpage_image] =>[orig_patent_app_number] => 12385454 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/385454
Pattern-producing method for semiconductor device Apr 7, 2009 Issued
Array ( [id] => 7680893 [patent_doc_number] => 20100023915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Calculation System For Inverse Masks' [patent_app_type] => utility [patent_app_number] => 12/416016 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 23568 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12416016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416016
Calculation System For Inverse Masks Mar 30, 2009 Abandoned
Array ( [id] => 4500881 [patent_doc_number] => 07904871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Computer-implemented method of optimizing refraction and TIR structures to enhance path lengths in PV devices' [patent_app_type] => utility [patent_app_number] => 12/407602 [patent_app_country] => US [patent_app_date] => 2009-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 32020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904871.pdf [firstpage_image] =>[orig_patent_app_number] => 12407602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/407602
Computer-implemented method of optimizing refraction and TIR structures to enhance path lengths in PV devices Mar 18, 2009 Issued
Array ( [id] => 6524406 [patent_doc_number] => 20100231261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Apparatus and Method for Mixed Single-Rail and Dual-Rail Combinational Logic with Completion Detection' [patent_app_type] => utility [patent_app_number] => 12/402265 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5004 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20100231261.pdf [firstpage_image] =>[orig_patent_app_number] => 12402265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402265
Apparatus and method for mixed single-rail and dual-rail combinational logic with completion detection Mar 10, 2009 Issued
Array ( [id] => 8297461 [patent_doc_number] => 08225261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Methods for defining contact grid in dynamic array architecture' [patent_app_type] => utility [patent_app_number] => 12/399948 [patent_app_country] => US [patent_app_date] => 2009-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8606 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12399948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399948
Methods for defining contact grid in dynamic array architecture Mar 6, 2009 Issued
Array ( [id] => 4441447 [patent_doc_number] => 07971163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Property generating apparatus, property generating method and program' [patent_app_type] => utility [patent_app_number] => 12/391752 [patent_app_country] => US [patent_app_date] => 2009-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971163.pdf [firstpage_image] =>[orig_patent_app_number] => 12391752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/391752
Property generating apparatus, property generating method and program Feb 23, 2009 Issued
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