Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7542996 [patent_doc_number] => 08060845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Minimizing impact of design changes for integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/173222 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2651 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060845.pdf [firstpage_image] =>[orig_patent_app_number] => 12173222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173222
Minimizing impact of design changes for integrated circuit designs Jul 14, 2008 Issued
Array ( [id] => 288684 [patent_doc_number] => 07552413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model' [patent_app_type] => utility [patent_app_number] => 12/166811 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3774 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552413.pdf [firstpage_image] =>[orig_patent_app_number] => 12166811 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166811
System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model Jul 1, 2008 Issued
Array ( [id] => 4637062 [patent_doc_number] => 08015527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Routing of wires of an electronic circuit' [patent_app_type] => utility [patent_app_number] => 12/166012 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5848 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015527.pdf [firstpage_image] =>[orig_patent_app_number] => 12166012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166012
Routing of wires of an electronic circuit Jun 30, 2008 Issued
Array ( [id] => 4621761 [patent_doc_number] => 08001492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Evaluation method for interconnects interacted with integrated-circuit manufacture' [patent_app_type] => utility [patent_app_number] => 12/215552 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5362 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001492.pdf [firstpage_image] =>[orig_patent_app_number] => 12215552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215552
Evaluation method for interconnects interacted with integrated-circuit manufacture Jun 26, 2008 Issued
Array ( [id] => 4684140 [patent_doc_number] => 20080250366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'NOISE CHECKING METHOD AND APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH NOISE CHECKING PROGRAM IS STORED' [patent_app_type] => utility [patent_app_number] => 12/141392 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17727 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250366.pdf [firstpage_image] =>[orig_patent_app_number] => 12141392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141392
Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored Jun 17, 2008 Issued
Array ( [id] => 7548061 [patent_doc_number] => 08056042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Automatic delay adjusting method for semiconductor integrated circuit by using dummy wiring' [patent_app_type] => utility [patent_app_number] => 12/213372 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 5729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056042.pdf [firstpage_image] =>[orig_patent_app_number] => 12213372 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213372
Automatic delay adjusting method for semiconductor integrated circuit by using dummy wiring Jun 17, 2008 Issued
Array ( [id] => 4712280 [patent_doc_number] => 20080300806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Power consumption calculating method' [patent_app_type] => utility [patent_app_number] => 12/155082 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7132 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20080300806.pdf [firstpage_image] =>[orig_patent_app_number] => 12155082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155082
Power consumption calculating method May 28, 2008 Abandoned
Array ( [id] => 5491437 [patent_doc_number] => 20090292508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'METHOD AND APPARATUS FOR MODELING LONG RANGE EUVL FLARE' [patent_app_type] => utility [patent_app_number] => 12/126152 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20090292508.pdf [firstpage_image] =>[orig_patent_app_number] => 12126152 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126152
Method and apparatus for modeling long-range EUVL flare May 22, 2008 Issued
Array ( [id] => 4443782 [patent_doc_number] => 07900174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method and system for characterizing an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/152932 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6752 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900174.pdf [firstpage_image] =>[orig_patent_app_number] => 12152932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/152932
Method and system for characterizing an integrated circuit design May 18, 2008 Issued
Array ( [id] => 4841724 [patent_doc_number] => 20080282210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'System And Method For Product Yield Prediction' [patent_app_type] => utility [patent_app_number] => 12/119862 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282210.pdf [firstpage_image] =>[orig_patent_app_number] => 12119862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119862
System and method for product yield prediction May 12, 2008 Issued
Array ( [id] => 9940925 [patent_doc_number] => 08990757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Dedicated interface architecture for a hybrid integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/114143 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 3827 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12114143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114143
Dedicated interface architecture for a hybrid integrated circuit May 1, 2008 Issued
Array ( [id] => 4582577 [patent_doc_number] => 07840930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Signal connection program, method, and device of hierarchical logic circuit' [patent_app_type] => utility [patent_app_number] => 12/102462 [patent_app_country] => US [patent_app_date] => 2008-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 9210 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840930.pdf [firstpage_image] =>[orig_patent_app_number] => 12102462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/102462
Signal connection program, method, and device of hierarchical logic circuit Apr 13, 2008 Issued
Array ( [id] => 4815358 [patent_doc_number] => 20080195989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/101599 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195989.pdf [firstpage_image] =>[orig_patent_app_number] => 12101599 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101599
Content based yield prediction of VLSI designs Apr 10, 2008 Issued
Array ( [id] => 6234631 [patent_doc_number] => 20100185996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'SEMICONDUCTOR LAYOUT SCANNING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/593392 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4355 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185996.pdf [firstpage_image] =>[orig_patent_app_number] => 12593392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/593392
Semiconductor layout scanning method and system Mar 18, 2008 Issued
Array ( [id] => 5535427 [patent_doc_number] => 20090235215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/047566 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235215.pdf [firstpage_image] =>[orig_patent_app_number] => 12047566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047566
Gridded glyph geometric objects (L3GO) design method Mar 12, 2008 Issued
Array ( [id] => 4602990 [patent_doc_number] => 07979835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method of estimating resource requirements for a circuit design' [patent_app_type] => utility [patent_app_number] => 12/041182 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979835.pdf [firstpage_image] =>[orig_patent_app_number] => 12041182 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041182
Method of estimating resource requirements for a circuit design Mar 2, 2008 Issued
Array ( [id] => 4700403 [patent_doc_number] => 20080222587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Integrated Circuit Cell Library for Multiple Patterning' [patent_app_type] => utility [patent_app_number] => 12/041584 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9508 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222587.pdf [firstpage_image] =>[orig_patent_app_number] => 12041584 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041584
Integrated circuit cell library for multiple patterning Mar 2, 2008 Issued
Array ( [id] => 5393529 [patent_doc_number] => 20090210842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Automated Method for Buffering in a VLSI Design' [patent_app_type] => utility [patent_app_number] => 12/032762 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210842.pdf [firstpage_image] =>[orig_patent_app_number] => 12032762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032762
Automated method for buffering in a VLSI design Feb 17, 2008 Issued
Array ( [id] => 4724864 [patent_doc_number] => 20080204405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Method and System of Displaying an Exposure Condition' [patent_app_type] => utility [patent_app_number] => 12/031782 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4531 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20080204405.pdf [firstpage_image] =>[orig_patent_app_number] => 12031782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031782
Method and system of displaying an exposure condition Feb 14, 2008 Issued
Array ( [id] => 5393534 [patent_doc_number] => 20090210847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION' [patent_app_type] => utility [patent_app_number] => 12/031992 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4769 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210847.pdf [firstpage_image] =>[orig_patent_app_number] => 12031992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/031992
Synchronous to asynchronous logic conversion Feb 14, 2008 Issued
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