Search

Leigh M. Garbowski

Examiner (ID: 18821, Phone: (571)272-1893 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2764, 2825, 2763, 2768, 2304
Total Applications
1705
Issued Applications
1528
Pending Applications
70
Abandoned Applications
125

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5393527 [patent_doc_number] => 20090210840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Optimization Method of Integrated Circuit Design for Reduction of Global Clock Load and Balancing Clock Skew' [patent_app_type] => utility [patent_app_number] => 12/032542 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4589 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210840.pdf [firstpage_image] =>[orig_patent_app_number] => 12032542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032542
Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew Feb 14, 2008 Issued
Array ( [id] => 4730894 [patent_doc_number] => 20080209366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD AND APPARATUS FOR ANALYZING CIRCUIT MODEL BY REDUCTION AND COMPUTER PROGRAM PRODUCT FOR ANALYZING THE CIRCUIT MODEL' [patent_app_type] => utility [patent_app_number] => 12/027732 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5642 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209366.pdf [firstpage_image] =>[orig_patent_app_number] => 12027732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/027732
Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model Feb 6, 2008 Issued
Array ( [id] => 4787654 [patent_doc_number] => 20080140983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX' [patent_app_type] => utility [patent_app_number] => 12/020879 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7994 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140983.pdf [firstpage_image] =>[orig_patent_app_number] => 12020879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020879
Affinity-based clustering of vectors for partitioning the columns of a matrix Jan 27, 2008 Issued
Array ( [id] => 7595653 [patent_doc_number] => 07620929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Programmable logic device having a programmable selector circuit' [patent_app_type] => utility [patent_app_number] => 12/020712 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620929.pdf [firstpage_image] =>[orig_patent_app_number] => 12020712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/020712
Programmable logic device having a programmable selector circuit Jan 27, 2008 Issued
Array ( [id] => 4602989 [patent_doc_number] => 07979834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Predicting timing degradations for data signals in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/018992 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979834.pdf [firstpage_image] =>[orig_patent_app_number] => 12018992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018992
Predicting timing degradations for data signals in an integrated circuit Jan 23, 2008 Issued
Array ( [id] => 5354939 [patent_doc_number] => 20090186283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Photomasks and Methods Of Forming Photomasks' [patent_app_type] => utility [patent_app_number] => 12/018612 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4928 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20090186283.pdf [firstpage_image] =>[orig_patent_app_number] => 12018612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018612
Methods of forming photomasks Jan 22, 2008 Issued
Array ( [id] => 4500841 [patent_doc_number] => 07904865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Placement driven routing' [patent_app_type] => utility [patent_app_number] => 12/018422 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4256 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904865.pdf [firstpage_image] =>[orig_patent_app_number] => 12018422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018422
Placement driven routing Jan 22, 2008 Issued
Array ( [id] => 4600870 [patent_doc_number] => 07984406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Timing verification method and apparatus' [patent_app_type] => utility [patent_app_number] => 12/010202 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984406.pdf [firstpage_image] =>[orig_patent_app_number] => 12010202 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010202
Timing verification method and apparatus Jan 21, 2008 Issued
Array ( [id] => 4600853 [patent_doc_number] => 07984395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Hierarchical compression for metal one logic layer' [patent_app_type] => utility [patent_app_number] => 12/016072 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4488 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984395.pdf [firstpage_image] =>[orig_patent_app_number] => 12016072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016072
Hierarchical compression for metal one logic layer Jan 16, 2008 Issued
12/009402 ALGORITHMIC FABRICATION OF ELECTRONIC COMPONENTS Jan 16, 2008 Abandoned
Array ( [id] => 5358173 [patent_doc_number] => 20090032967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Semiconductor Device with Dynamic Array Section' [patent_app_type] => utility [patent_app_number] => 12/013342 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 76 [patent_no_of_words] => 32635 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20090032967.pdf [firstpage_image] =>[orig_patent_app_number] => 12013342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013342
Semiconductor device with dynamic array section Jan 10, 2008 Issued
Array ( [id] => 7518006 [patent_doc_number] => 08042088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Method and system for implementing stacked vias' [patent_app_type] => utility [patent_app_number] => 11/965712 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4887 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/042/08042088.pdf [firstpage_image] =>[orig_patent_app_number] => 11965712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965712
Method and system for implementing stacked vias Dec 26, 2007 Issued
Array ( [id] => 5504265 [patent_doc_number] => 20090164953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Simultaneous optimization of analog design parameters using a cost function of responses' [patent_app_type] => utility [patent_app_number] => 12/004862 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2306 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164953.pdf [firstpage_image] =>[orig_patent_app_number] => 12004862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004862
Simultaneous optimization of analog design parameters using a cost function of responses Dec 20, 2007 Issued
Array ( [id] => 4487565 [patent_doc_number] => 07870526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Aid apparatus, computer-readable recording medium in which design aid program is stored, and interactive design aid apparatus' [patent_app_type] => utility [patent_app_number] => 11/961042 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870526.pdf [firstpage_image] =>[orig_patent_app_number] => 11961042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961042
Aid apparatus, computer-readable recording medium in which design aid program is stored, and interactive design aid apparatus Dec 19, 2007 Issued
Array ( [id] => 4966955 [patent_doc_number] => 20080109775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Combined memories in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/004292 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5583 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109775.pdf [firstpage_image] =>[orig_patent_app_number] => 12004292 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004292
Combined memories in integrated circuits Dec 18, 2007 Issued
Array ( [id] => 146883 [patent_doc_number] => 07689964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'System and method for routing connections' [patent_app_type] => utility [patent_app_number] => 11/960452 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689964.pdf [firstpage_image] =>[orig_patent_app_number] => 11960452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960452
System and method for routing connections Dec 18, 2007 Issued
Array ( [id] => 5424378 [patent_doc_number] => 20090150834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'METHOD OF REUSING CONSTRAINTS IN PCB DESIGNS' [patent_app_type] => utility [patent_app_number] => 11/954092 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2476 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150834.pdf [firstpage_image] =>[orig_patent_app_number] => 11954092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954092
Method of reusing constraints in PCB designs Dec 10, 2007 Issued
Array ( [id] => 4936833 [patent_doc_number] => 20080074147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'WIRING OPTIMIZATIONS FOR POWER' [patent_app_type] => utility [patent_app_number] => 11/952544 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11704 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074147.pdf [firstpage_image] =>[orig_patent_app_number] => 11952544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952544
Wiring optimizations for power Dec 6, 2007 Issued
Array ( [id] => 4455150 [patent_doc_number] => 07966586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Intelligent pattern signature based on lithography effects' [patent_app_type] => utility [patent_app_number] => 11/952912 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2775 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966586.pdf [firstpage_image] =>[orig_patent_app_number] => 11952912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952912
Intelligent pattern signature based on lithography effects Dec 6, 2007 Issued
Array ( [id] => 4923885 [patent_doc_number] => 20080072202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'TECHNIQUES FOR SUPER FAST BUFFER INSERTION' [patent_app_type] => utility [patent_app_number] => 11/947706 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7034 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072202.pdf [firstpage_image] =>[orig_patent_app_number] => 11947706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947706
Techniques for super fast buffer insertion Nov 28, 2007 Issued
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